As a Sr Principal Design Engineer at Cadence, you will lead the Design Verification (DV) execution of UCIe PHY IP. This includes driving internal DV team meetings, collaborating with RTL, AMS system modeling, and PD teams. You will be responsible for defining and architecting verification environments and methodologies, and improving existing verification methodologies such as Co-Simulation (Co-SIM), UPF Power Aware Simulations (UPF PA Sim), VIP/DIP integration and Verification, and Formal Verification, with a focus on continuous improvement. You will analyze execution and quality issues and develop new functional verification methodologies.