SRAM Circuit Design Engineer - New College Graduate 2025

NVIDIA's Digital IP (DIP) group is seeking a skilled SRAM Circuit Design Engineer to develop sophisticated SRAM compilers and embedded SRAMs for advanced FinFET processes. This role involves transistor-level circuit design, layout supervision, physical and logical verification, and automation of SRAM macro assembly and validation. The engineer will also explore future process nodes to optimize power, performance, and area characteristics, contributing to world-changing products.

Must Have

• 0-4 years of SRAM design experience with strong background in digital circuit design, layout, and validation on advanced FinFET processes
• Prior design experience in single-port, dual-port, or register file SRAM-based macros, including complex circuits like self-timed logic and sense-amplifiers
• Python scripting ability to parse data and automate tasks
• Successful track record of delivering designs to production

Good to Have

• Self-motivation, attention to detail, and good written, verbal, and presentation skills
• High degree of scripting expertise in Python
• Familiarity with Cadence schematic and layout capture tools
• Silicon testing/debug experience

The Digital IP (DIP) group at NVIDIA is an organization of circuit design and CAD engineers that creates a wide variety of IP for the chips NVIDIA designs. This group works closely with internal SOC design, silicon testing, and productization teams that turn our IP into products that change the world. One of the roles fulfilled by the DIP group is to develop sophisticated SRAM compilers that are used extensively by our SOC design partners. We are looking to hire a skilled and creative SRAM circuit designer to help achieve these goals in a high-visibility position.

What you'll be doing:

• Embedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros.
• SRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros using NVIDIA's extensive compute resources.
• Advanced development: Exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics.

What we need to see:

• BSEE minimum (or equivalent experience), MSEE preferred
• 0-4 years of SRAM design experience with a strong background in digital circuit design, layout, and validation on advanced FinFET processes
• Prior design experience in single-port, dual-port, or register file SRAM-based macros required, including complex circuits like self-timed logic and sense-amplifiers
• Python scripting ability to parse data and automate tasks
• Successful track record of delivering designs to production

Ways to stand out from the crowd:

• Self-motivation, attention to detail, and good written, verbal, and presentation skills are needed to success in this role
• A high degree of scripting expertise in Python
• Familiarity with Cadence schematic and layout capture tools
• Silicon testing/debug experience