Test Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As a test development senior staff engineer in the Operations business group, you will test features on the silicon semiconductor chips Marvell produces for internal and external customers. You will make sure we don’t ship out any underperforming units. You’ll work closely with design to make sure their chip features are testable and that the results meet the customer’s specifications. You may even have to write new code or develop new testing strategies when our chips outpace the capabilities of current testing equipment.

We are seeking a skilled and motivated Test Engineer (TE) with hands-on experience in Co-Packaged Copper (CPC) technologies or a strong foundation in high-speed interconnects, SerDes testing, and system-level test development, as well as test hardware design, including load boards and sockets, with a focus on signal integrity (SI) and thermal design.
This role is critical in driving next-generation high-speed packaging and test strategies in collaboration with design, DFT, and product engineering teams.

What You Can Expect

• CPC: Develop and validate test programs for CPC-enabled silicon products at wafer and package level. Define and validate test hardware, including load boards for CPC environments
• Load Board & Hardware Design: Lead the design of load boards, including schematic definition, layout review, and bring-up. Select and validate high-performance sockets for CPC packages with high pin count and tight pitch. Evaluate and implement thermal solutions (e.g., active cooling, cold plates, thermal interface materials) to manage device power dissipation up to 1KW.
• Lead Cutting-Edge ATE Test Solutions: As a Senior Level Test Engineer, you will spearhead the development of ATE test solutions for characterization, production, and wafer sort on Advantest 93K and/or Teradyne tester platforms. Your work will be at the forefront of technology, ensuring our products meet the highest standards.
• Innovate High-Speed Testing Hardware: Design and develop advanced ATE test hardware for high-speed testing, pushing the boundaries of what's possible and ensuring our products are ready for the future.
• Craft Comprehensive Test Plans: Create detailed test plans and methodologies documentation that meet stringent product specifications, ensuring every product we release is of the highest quality.
• Collaborate with Cross-Functional Teams: Participate in testability and test plan reviews with DFx and Design teams, working together to define and enhance yield and test methodologies. Your input will be crucial in driving innovation and efficiency.
• Transform Test Patterns: Convert test patterns from the design simulation environment to ATE format, bridging the gap between design and production.
• Optimize and Innovate: Play a lead role in optimizing test flows, reducing test times, removing unnecessary steps, improving yields, and releasing production test programs in collaboration with product engineers. Your contributions will directly impact the efficiency and success of our products.
• Opportunities for Growth: At Marvell, we believe in nurturing talent and providing opportunities for professional development. As you excel in your role, you will have the chance to take on more responsibilities, lead larger projects, and advance your career within the company. We are committed to supporting your growth and helping you achieve your career goals.

What We're Looking For

• Bachelor's degree in electrical engineering or related fields.
• Master's degree in electrical engineering or related fields preferred.
• Experience with Co-Packaged Optics or Co-Packaged Copper integration and validation.
• Strong background in SerDes or high-speed interconnect testing (25G/50G/112G).
• Expertise in test program development on the Advantest 93K and/or Teradyne tester platform(s).
• Demonstrable experience in ATE testing (critical skill), test methodology, silicon process, DFT/DFM, and high-speed digital testing.
• Strong knowledge of C/C++, Perl, Python, and Linux environment.
• Effective interpersonal, teamwork, communication, and problem-solving skills.
• Highly motivated individual contributor with the ability to multitask in a fast-paced environment.

Expected Base Pay Range (USD)

115,790 - 173,500, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

#LI-VM1