Analog Engineer Intern - PhD

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Optical PHY (CE-OPHY) team designs high-speed and optical transceivers for communication infrastructure in long-haul, metro and datacenter. We address the bandwidth, capacity and power issues faced by cloud computing, mega data centers that powers the social media giant platforms. Our innovative approaches have resulted in the company’s products being first to market in many of key areas, developing the most advanced chips and subsystems solutions to address the ever-increasing demand of higher data rates driven by video-on demand, gaming and other real time data streams. We are seeking talented individuals to work on solving technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity.

What You Can Expect

• Design, simulate and verify analog blocks for industry leading optical transceivers
• Help test and characterize existing designs
• Work with custom layout engineers to implement designs
• System level/behavioral modeling

What We're Looking For

• Candidate MUST be currently pursuing an MS/PhD (preferred) degree in EE or related technical field(s)
• Candidate MUST have a deep and comprehensive understanding of analog integrated circuit fundamentals
• Research or Major design project experience in data conversion (i.e., ADC’s & DAC’s) interfaces
• Research or Major design project experience in high-speed analog front ends (i.e., CTLE’s, VGA’s, TAH/SAH’s)
• Research or Major design project experience in clock conditioning circuits (i.e., PLL’s, DLL’s, PI’s)
• Experience in behavioral modeling in Verilog-A and or System Verilog
• Experience in C, Python and Matlab programming/modeling in a Unix type environment
• Candidate MUST have a good understanding of signal processing fundamentals
• Candidate MUST have experience with CAD tools and simulators such as Cadence Virtuoso and Spectr

Expected Base Pay Range (USD)

31 - 61, $ per hour.

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

For Internship roles, we are proud to offer the following benefits package during the internship - medical, dental and vision coverage, perks and discount programs, wellness & mental health support including coaching and therapy, paid holidays, paid volunteer days and paid sick time. Additional compensation may be available for intern PhD candidates.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.