Responsibilities include building emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Developing, integrating, testing, and debugging hardware and software collateral in simulation, emulation, and FPGA models for testing new features. Writing directed tests, developing the test environment and hybrid emulation environment, and supporting verification of hardware and software/firmware. Defining and developing new capabilities and tools to achieve better verification through improved emulation and FPGA model usability. Enabling acceleration of RTL development and improving emulation/FPGA model usability for presilicon verification, post silicon validation, and software development. Developing improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Developing and utilizing automation aids, flows, and scripts in support of emulation utilization. Applying understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model). Collaborating with design, power and performance, silicon validation, and software teams, and participating in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues.