IP Design Verification Engineer

18 Minutes ago • 4 Years + • Quality Assurance • $153,540 PA - $216,770 PA

Job Summary

Job Description

This position is with the server group at Intel, focusing on developing and delivering Verification IPs. The role involves leading functional verification of IP logic blocks to ensure design compliance with specification requirements, driving comprehensive verification methodologies from planning through silicon validation. Key responsibilities include developing functional Verification IPs, performing functional verification, developing comprehensive IP verification plans, executing plans, debugging issues, and collaborating with various teams to enhance verification of complex architectural and microarchitectural features.
Must have:
  • Develop functional Verification IPs targeted for simulation and emulation testbench environments.
  • Perform functional verification of IP logic to ensure designs meet specification requirements and microarchitecture standards.
  • Develop comprehensive IP verification plans, test benches, and verification environments with full coverage analysis.
  • Execute verification plans and define system simulation and emulation models to verify design functionality and identify design issues.
  • Replicate, root cause, and debug issues in pre-silicon environments using advanced debugging methodologies.
  • Identify and implement corrective measures to resolve failing tests and improve overall design quality.
  • Collaborate with architects, RTL developers, and physical design teams to enhance verification of complex architectural and microarchitectural features.
  • Document detailed test plans and lead technical reviews with design and architecture teams to ensure verification completeness.
  • Maintain and continuously improve existing functional verification infrastructure, methodologies, and best practices.
  • Participate in defining verification infrastructure requirements and related Test Flow Methodologies (TFMs) for functional design verification.
  • Drive verification closure through systematic coverage analysis and regression testing protocols.
  • Bachelor's degree with 6+ years of experience OR Master's degree with 4+ years of experience in Computer Engineering, Computer Science, Electrical Engineering or related field.
  • Experience with C/C++ programming and Object-Oriented Software design, including algorithms and data structures.
  • Experience with software development practices and quality standards.
  • Experience with Unix/Windows-based software development tools.
  • Experience developing bus functional models for unit-level verification or Verification IP development.
Good to have:
  • Proficiency in SystemC, SystemVerilog, UVM, and ESL modeling methodologies.
  • Proficiency in hardware design and verification methodologies.
  • Working knowledge of high-speed hardware protocols (e.g., PCIe, UPI, DDR).
Perks:
  • Competitive pay
  • Stock
  • Bonuses
  • Health benefits
  • Retirement programs
  • Vacation

Job Details

This position is with the server group at Intel. This team is central team responsible for developing and delivering Verification IPs to server group.

Position Overview:

Lead functional verification of IP logic blocks to ensure design compliance with specification requirements, driving comprehensive verification methodologies from planning through silicon validation.

Key Responsibilities:

  • Develop functional Verification IPs targeted for simulation and emulation testbench environments
  • Perform functional verification of IP logic to ensure designs meet specification requirements and microarchitecture standards
  • Develop comprehensive IP verification plans, test benches, and verification environments with full coverage analysis
  • Execute verification plans and define system simulation and emulation models to verify design functionality and identify design issues
  • Replicate, root cause, and debug issues in pre-silicon environments using advanced debugging methodologies
  • Identify and implement corrective measures to resolve failing tests and improve overall design quality
  • Collaborate with architects, RTL developers, and physical design teams to enhance verification of complex architectural and microarchitectural features
  • Document detailed test plans and lead technical reviews with design and architecture teams to ensure verification completeness
  • Maintain and continuously improve existing functional verification infrastructure, methodologies, and best practices
  • Participate in defining verification infrastructure requirements and related Test Flow Methodologies (TFMs) for functional design verification
  • Drive verification closure through systematic coverage analysis and regression testing protocols

Qualifications:

Minimum Qualifications:

  • Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering or related field with 6+ years of experience -OR- Master's degree in Computer Engineering, Computer Science, Electrical Engineering or related field with 4+ years of experience

The experience must include:

  • C/C++ programming and Object-Oriented Software design, including algorithms and data structures
  • Software development practices and quality standards
  • Experience with Unix/Windows-based software development tools
  • Experience developing bus functional models for unit-level verification or Verification IP development

Preferred Qualifications:

  • Proficiency in SystemC, SystemVerilog, UVM, and ESL modeling methodologies
  • Proficiency in hardware design and verification methodologies
  • Working knowledge of high-speed hardware protocols (e.g., PCIe, UPI, DDR)

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

Business group:

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$153,540.00-$216,770.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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