Layout Engineer

2 Months ago • All levels • Software Development & Engineering

Job Summary

Job Description

Contribute to the architecture, design, and validation of radio transceivers integrated into complex wireless SoCs. Perform the layout and verification of custom RF and Analog IP for complex SoC products. Create detailed transistor-level layout of RF/analog circuit blocks such as LNA, Mixers, PLL, LO generation, Modulators, Power Amplifiers, ADC/DAC, Baseband Filters, Bandgap/Bias/LDO, etc. Integrate block-level and mid-level layouts through full verification flow, including DRC, LVS, DFM checks, and extractions. Work on top-level layout integration and verification. Liaise with the design team on critical circuit layout parameters and floor planning. Perform critical layout review of device placement, routings of power, ground, signals, and differential lines, and check of electro-migration, signal path, and signal coupling. Liaise with the design team to extract and optimize parasitic resistance and capacitance in the final layout. Provide schedule estimates and tracking information for project management. Liaise with CAD teams to resolve tool or flow issues. Liaise with the Technology team for the latest silicon learnings (best practices) and resolve PDK questions.

Job Details

APPLE INC has the following available in Austin, Texas. Contribute to the architecture, design, and validation of radio transceivers integrated into complex wireless SoCs. Perform the layout and verification of custom RF and Analog IP for complex SoC products. Create detailed transistor level layout of RF / analog circuit blocks such as LNA, Mixers, PLL, LO generation, Modulators, Power Amplifiers, ADC / DAC, Baseband Filters, Bandgap / Bias / LDO, etc. Integrate block-level and mid-level layouts through full verification flow, including DRC, LVS, DFM checks, and extractions. Work on top-level layout integration and verification. Liaise with the design team on critical circuit layout parameters and floor planning. Perform critical layout review of device placement, routings of power, ground, signals, and differential lines, and check of electro-migration, signal path, and signal coupling. Liaise with the design team to extract and optimize parasitic resistance and capacitance in the final layout. Provide schedule estimates and tracking information for project management. Liaise with CAD teams to resolve tool or flow issues. Liaise with the Technology team for the latest silicon learnings (best practices) and resolve PDK questions. 40 hours/week.

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