Pre-Silicon Verification Engineer

Job Description:

Role Overview

We are seeking a skilled Verif/Validation Engineer with expertise in developing testbenches for pre-silicon verification. The role involves building scalable verification environments, creating stimulus, monitoring functionality, and ensuring coverage closure using industry-standard methodologies.

Key Responsibilities

• Develop SystemVerilog/UVM-based testbenches for IP, subsystem, or SoC-level verification.
• Create and maintain verification plans, test cases, and coverage models.
• Implement and integrate scoreboards, monitors, checkers, assertions, and transactors for functional correctness.
• Work with Verification IP (VIP) for industry-standard protocols (AMBA, UCIe, PCIe, DDR, Ethernet, etc.) and integrate them into testbenches.
• Build reusable constrained-random and directed test scenarios.
• Debug failures, perform root cause analysis, and work closely with design and architecture teams.
• Analyze functional coverage, code coverage, and assertion coverage to ensure verification completeness.
• Participate in design/verification reviews and contribute to methodology improvements.
• Automate regression runs and maintain CI verification flows (Jenkins, Git, etc. if applicable).

Qualifications:

Required Skills & Qualifications:

• Bachelor’s/Master’s in Electrical/Electronics/Computer Engineering or related field with 8+ years of experience.
• Strong hands-on experience with SystemVerilog and UVM methodology.
• Proven experience in transactor modeling and VIP integration/customization.
• Good understanding of digital design fundamentals (RTL, FSMs, buses, etc.).
• Familiarity with coverage-driven verification and constraint random test generation.
• Proficiency with industry-standard simulators and/or emulators (Synopsys VCS/Zebu, Cadence Xcelium/Palladium, Mentor Questa/Veloce, etc.).
• Debugging skills using waveforms and verification tools.
• Exposure to SVA (SystemVerilog Assertions) and functional coverage techniques.
• Experience with C/C++/Python for testbench integration or automation.
• Hands-on work with protocol VIPs (AXI, AHB, APB, UCIe, PCIe, DDR, Ethernet, USB, etc.).
• Strong communication and teamwork skills.
• Experience in applying AI tools for verification/validation is a plus

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.