Senior Staff Engineer, Physical Design

1 Month ago • 3-10 Years • Software Development & Engineering • $125,900 PA - $186,260 PA

Job Summary

Job Description

This role focuses on the physical design and methodology for future high-performance processor chips. Responsibilities include working with design teams, implementing designs using EDA tools, driving assembly and design closure with RTL teams, and mentoring junior employees. The role involves using industry-standard EDA tools and scripting languages like Shell, Python, and TCL. The job requires expertise in back-end physical design, full-chip integration, experience with digital design environments, and a good understanding of RTL to GDS flows.
Must have:
  • 5+ years of back-end physical design experience.
  • Experience in full-chip & sub-hierarchy integration.
  • Good scripting skills in Perl, tcl and Python.
Good to have:
  • Experience with multi-voltage and low-power design techniques is a plus.
  • Experience with Cadence Innovus is preferred.
Perks:
  • Flexible time off
  • 401k
  • Year-end shutdown
  • Floating holidays
  • Paid time off to volunteer

Job Details

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications.

What You Can Expect

  • This role is based in Austin, TX. You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. This position also provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.

  • Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner.

  • Implement/support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools.

  • Work with RTL design teams to drive assembly and design closure.

  • Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes.

  • Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation.

What We're Looking For

  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.

  • 5+ years experience in back-end physical design and verification.

  • Expertise in full-chip & sub-hierarchy integration preferred.

  • Experience integrating and taping out large designs utilizing a digital design environment.

  • Good understanding of RTL to GDS flows and methodology.

  • Good scripting skills in Perl, tcl and Python.

  • Strong knowledge in static timing analysis (Primetime) preferred.

  • Understanding of digital logic and computer architecture.

  • Knowledge of Verilog.

  • Good communication skills and self-discipline contributing in a team environment.

  • Experience with multi-voltage and low-power design techniques is a plus.

  • Experience with Cadence Innovus is preferred.

Expected Base Pay Range (USD)

125,900 - 186,260, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements 

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

#LI-VM1

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About The Company

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

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