Senior Staff Physical Design Engineer

Your Team, Your Impact

Group Description

The Marvell Physical Design team is located in our Burlington, VT office, and has a long history of successful design tapeouts in advanced process nodes. Our team is made up of both newer and more experienced engineers with a broad depth of physical design engineering experience. Being a part of our team will give you a chance to work on many different aspects of the chip design process, while working alongside some of the best engineers in the industry. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor and data center chips in a leading-edge CMOS process technology.

What You Can Expect

In this role based in our Burlington, VT location. You will work on Marvell's high-performance, cutting-edge chips in physical design of complex chips as well as contribute towards methodology to enable an efficient and robust design process. Your tasks will include performing synthesis, place and route, clock tree synthesis, routing, power-signal integrity, and physical verification as well as timing analysis and closure on multiple intermediate and complex logic blocks with IP challenges. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. This role will expose you to partition and chip-level issues to resolve. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
• Strong understanding of standard RTL to GDS flows and methodology.
• Strong proficiency of PD optimization and Routing such as floorplanning, placement, clocking, and routing.
• Strong knowledge of placement with complex IP such as DDR, PCIe, etc.
• Has been a leader in their physical design block team to report the status of team's block QoR and assist with the team's challenges preferred.
• Has some exposure of partition level work.
• Has some exposure to Siemens Tessent DFT preferred.
• Strong proficiency with EDA tools such as Cadence Innovus / Synopsys Fusion Compiler.
• Proficient with Synthesis and Timing EDA tools.
• Good scripting skills in languages such as Perl, tcl, and Python.
• Good object-oriented programming skills.
• Good understanding of digital logic and computer architecture.
• Knowledge of Verilog/VHDL.
• Good communication skills and self-discipline contributing in a team environment.

Expected Base Pay Range (USD)

125,900 - 186,260, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.