Senior Staff STA CAD Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

About Marvell Marvell is empowering the global data economy. Whether at the network core or edge, our leadership technologies make it possible for the world’s data to be processed, moved, stored and secured faster and more reliably. With leading intellectual property and deep system-level knowledge, Marvell's infrastructure semiconductor solutions are transforming the 5G, cloud, enterprise and automotive markets of tomorrow.At Marvell, you’ll see your ideas put to work, share in the success of our company, and achieve a healthy life-work balance in a strong culture of corporate citizenship and global semiconductor leadership. If you are ready to excel, innovate, and truly enjoy where you work, apply now for Web Creative Director position and join Marvell’s growing Global Corporate Marketing and Communications organization. This opening is part the Central Engineering CAD & design services (CCDS).

What You Can Expect

• Develop ,maintain and lead signoff static timing analysis (STA) and timing ECO flows addressing the needs of Marvell’s various Business Units
• Contribute to the deployment and support of these flows
• Work in collaboration with the rest of the team to ensure optimal integration inside the overall CAD platform
• Come-up with innovative solutions to ever-increasing design challenges
• Keep up with process and tool evolutions.
• Interface with EDA vendors for optimal tool usage.

What We're Looking For

• BS/MS in EE/CS with 10+ years of hands-on experience in Signoff STA, extraction, and timing ECO flows and methodology.
• Recent experience with either Cadence Tempus or Synopsys PT-SI (experience with both is a plus).
• Solid understanding of Timing constraints quality assessment, Timing analysis and debug.
• Timing Correlation between tools
• Solid understanding of timing variation aspects and it’s impact on timing analysis
• Block-level and chip-level signoff STA
• Block and chip-level timing ECOs and feedback into physical implementation system
• Signoff power analysis and optimization
• Handling of multi-voltage designs in signoff STA
• Knowledge of Place and Route (P&R) especially understanding of physical impacting in implementing timing ECOs
• Excellent proficiency in Tcl scripting in the context of flow development.
• Demonstrate good analysis and problem-solving skills. Out-of-the-box thinking
• Team player with good verbal and written communication skills
• Ability to run the following tasks is a plus: SDC linting and constraints checking tools ,P&R ,EM/IR
• Experience with EDA tool benchmarks

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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