SoC RTL Security Design Engineer

2 Months ago • 3-5 Years • Research Development • $132,000 PA - $189,000 PA

Job Summary

Job Description

This SoC RTL Security Design Engineer role involves creating and reviewing security subsystem design specifications, developing SystemVerilog RTL for ASIC products, collaborating with architecture and power teams to evaluate security features, working with design validation teams on test plans, and ensuring designs meet physical requirements. The position requires RTL design expertise and the ability to lead multifaceted efforts with various stakeholders. You'll contribute to SoC-level RTL design for data center accelerators, focusing on management and control subsystems, and developing foundational SoC infrastructure (security, clocking, etc.). This highly cross-functional role necessitates coordination with software and system hardware teams.

Must have:

3+ years RTL coding (Verilog/SystemVerilog)
Experience with EDA tools
Security design experience
SystemVerilog RTL development
Collaboration with cross-functional teams

Good to have:

Master's/PhD in relevant field
Experience with security IPs
Scripting languages (Tcl, Python, Perl)
Understanding of digital design fundamentals

Perks:

Bonus
Equity
Benefits

5 skills required

5 skills required for this role

Add these skills to join the top 1% applicants for this job

python

perl

foundation

innovation

cross-functional

Job Details

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
3 years of experience with RTL coding using Verilog/SystemVerilog.
Experience with industry-standard EDA tools for simulation, synthesis and power analysis.

Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
5 years of experience in ASIC design with 3 years of experience working on security design.
Experience interacting with software, system hardware, and other cross-functional teams.
Experience developing and integrating security IPs into an SoC.
Experience with scripting languages (e.g., Tcl, Python or Perl).
Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines and bus protocols.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a SoC Design Engineer, you will join a team working on SoC-level RTL design for our data center accelerators. You will design RTL IP with the focus on management and control subsystem, also participate in developing infrastructure and methodology that form the foundation of our SoCs (i.e., security, clocking, reset, error handling, debug, chip management and SOC chassis etc.). You will build a global understanding of how our accelerators are built from concept to production. This is a highly cross-functional role that will require you to coordinate and co-design with our software and system hardware counterparts. In this role, you will utilize, a background in RTL design, and the ability to lead multi-faceted efforts involving many stakeholders.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about .

Responsibilities

Create and review the security subsystem's design microarchitecture specifications.
Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
Work with architecture and power teams to evaluate security features and their impact.
Work with design validation (DV) teams to create test plans to verify, and debug design RTL.
Work with physical design teams to ensure design meets physical requirements and timing closure.