Job Description
- Familiarity with GLS, simulation, UVM, OVM methodologies.
- Develop and verify RTL for digital and memory subsystems, including BIST.
- Perform DFT insertion and verification signoff for IO, ARM-PNR, Memory Digital Subsystems with Tessent/Embedded MBIST.
- Conduct MBIST, ATPG, RSQ Verification and sign-off.
- Execute formal verification, Cross Clock Domain checks, and Power/Timing sign off.
- Verify complex Digital subsystems using OVM, UVM methodology, and create verification suites.
- Hands-on experience with RTL and Synthesis.
- Hands-on experience in defining ICC/Synthesis constraints for timing closure.
- Familiarity with DFT flows including MBIST, ATPG, RSQ, and verification methodologies.
- Familiarity with Spyglass, LEC, CDC, and Synthesis tools like DC Ultra, Fusion Compiler.
- Proficiency with Verilog NC, Verilog XL tools.
- Strong fundamentals in digital design and coding/verifying complex RTL subsystems.
Broadcom Central Engineering team is looking for a Multi Skilled RTL, Verification engineer with DFT expertise. The Successful candidate will work in one or more domains of RTL, Verification, DFT for Complex Memory, IO subsystems, Hierarchical Blocks including BIST. It is great Opportunity and challenging role for the people who wants to gain in depth knowledge on end to end Chip development flow with Deeper Expertise on DFT and Memory BIST, eBIST.
Subsystem RTL, Verification Engineer
1. RTL development and Verification for Digital subsystems, Memory Subsystems including BIST.
2. DFT Insertion and Verification signoff for IO, ARM-PNR, Memory Digital Subsystems with Tessent/Embedded MBIST
3. MBIST, ATPG, RSQ Verification and sign-off.
4. Formal verification, Cross Clock Domain checks, Power/Timing sign off
5. Verify complex Digital subsystems through OVM, UVM methodology, creating the Verification Suit Independently.
Skillset:
1. Hands on Experience with RTL, Synthesis,
2. Hands on experience in defining ICC/Synthesis constraints that meets timing closure needs
3. Familiarity with DFT flows includes MBIST, ATPG, RSQ and Verification methodologies and best practices for the DFT signoff.
4. Familiarity with Spyglass, LEC, CDC, and Synthesis tools DC Ultra, Fusion Compiler.
5. Familiarity with GLS, simulation, UVM, OVM methodologies is a big plus
6. Proficiency with Verilog NC, Verilog XL tools
7. Strong fundamentals in digital design and Coding/Verifying complex RTL subsystems
