As a VLSI CAD Engineer at Apple in Austin, Texas, you will design and manufacture next-generation, high-performance, power-efficient processors and systems-on-chip (SoC). You will script in TCL or Perl, managing trade-offs in product success metrics, particularly for on-device Machine Learning constraints. This role involves debugging Mixed Signal QA flows and Physical Design (PD) flows, utilizing expertise in floor planning, placement, optimization, clocking, and routing. You will develop innovative solutions for physical design and optimization, collaborating with cross-functional teams to address key physical design challenges. Additionally, you will develop methodologies for low-power designs, working with tools like Physical Design Verification, RC extraction, IR, and Static Timing Analysis (STA). Your responsibilities include developing flows for innovative technologies with industry-standard Placement and Routing tools, supporting implementation flows, and creating flows for improved Power, Performance, and Area (PPA) and productivity, including Machine Learning based solutions. You will also work with tool vendors to resolve tool/flow issues and develop/maintain custom CAD tools for implementation and signoff within CAD Place and Route flows. This is a full-time position requiring 40 hours per week.