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The DRAM Design Lab (DDL) is part of Samsung’s Memory Business Unit and focuses on developing next-generation DRAM solutions. The Senior Engineer will be designing High Bandwidth Memory (HBM) product, developing DRAM architecture, and managing customer interactions throughout the design process. Responsibilities include developing and optimizing DRAM architecture, leading design specifications, collaborating with cross-functional teams, and analyzing electrical data. The position is based in San Jose, CA and requires daily onsite presence.

Staff Engineer, AI/ML Software Compiler

<div>Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.&nbsp; Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.&nbsp; We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.</div><div>What You’ll Do The DRAM Design Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash.&nbsp; DDL’s vision is to solve key problems in developing next-generation DRAM solutions, including High Bandwidth Memory (HBM). We are an integral part of Samsung’s strong R&amp;D focus and lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps. Come join the team that is designing HBM product, developing DRAM architecture, co-working head office and managing customer in all stages of design. You’ll focus on enhancement of full chip sim check, DFT consultation, IDD / PDN / checking reliability by developing the architecture of DRAM and optimize it for mass production. Location: Daily onsite presence at our San Jose, CA headquarters in alignment with our Flexible Work policy <ul> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Develop DRAM architecture and optimize floorplan for next generation DRAM</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Lead design specification, performance analysis and test plan etc.</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Technical interactions with internal and external customers</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Develop ROW, Column Bank architecture design and related test modes</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Develop methods to reduce DRAM power consumption</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Analyze electrical data from Si and validate new core design architecture performance</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Develop and implement a DFT architecture and methodology for the product</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Power delivery network floor planning and optimization</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Collaboratively design with cross-functional teams, such as product managers, engineers, and marketers, to ensure that designs align with the product vision and strategy</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Identify device requirements for the advanced memory product design</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Collaborate with process integration, quality assurance, product engineering and modeling group for DRAM design architecture and technology optimization</li> </ul> What You Bring <ul> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">PhD with 0+ years of experience in DRAM or related technical field preferred.</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Graduation date between May 2024 - May 2025 required</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Required knowledge, achievements, and skillsets in memory design.</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Proficient with design software and statistical analysis tools.</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Comprehensive understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Expertise in DRAM product development (DDRx, GDDRx, LPDDRx, HBMx, etc.) preferred</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Strong experience in DRAM I/O interfaces and SERDES preferred</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Proficiency in DRAM full chip functional verification preferred</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Demonstrated track record of innovation and creativity in problem solving</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">You’re inclusive, adapting your style to the situation and diverse global norms of our people.</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.</li> <li style="font-family: arial, helvetica, sans-serif; font-size: 10pt;">Innovative and creative, you proactively explore new ideas and adapt quickly to change.</li> </ul> &nbsp; #LI-AD1</div><div class="job__pay-ranges"><div class="pay-range"><div class="description"><div class="body">What We Offer The pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on a number of factors—including the role’s function and location, as well as the individual’s knowledge, skills, experience, education, and training. We also offer incentive opportunities that reward employees based on individual and company performance.&nbsp; This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community. Enjoy Time Away You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge. Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and an errand service. Prioritize Emotional Wellness With on-demand apps and paid therapy sessions, you’ll have support no matter where you are. Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier. Embrace Flexibility Benefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you.</div></div>Base Pay Range$134,400 - $201,600 USD</div></div><div>Equal Opportunity Employment Policy&nbsp; Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Covid-19 Policy To help keep our employees, customers, and communities safe, we've developed guidelines for our team. Currently, we encourage vaccination for all employees and may require it depending on job functions (e.g., traveling for business, meeting with customers). While visiting our offices or attending team events, we ask employees to complete a daily health questionnaire and complete a weekly COVID test. Our COVID policies are subject to change depending on public health, regulatory, and business circumstances.&nbsp; Applicant Privacy Policy https://semiconductor.samsung.com/us/careers/privacy &nbsp;</div></div>

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