ASIC RTl(DSP) design engineer/Sr Lead/staff/Sr Staff

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Minimum Qualifications

• Previous experience working on complex high-performance RTL design, preferably on DSP or processor based sub-system.
• Expert in hardware (RTL) design in Verilog, System Verilog or VHDL.
• Knowledge of standard on chip bus interface protocols (AXI, APB, AHB)
• Experience with some of below.
• Model development (SystemC, or C++)
• RTL to gates synthesis (Synopsys DCG or Cadence Genus)
• Design rule and CDC checking (SVA assertions, Spyglass, 0-in)
• Work on high performance  low power RTL design.
• Scripting languages (PERL, Python, TCL, C, etc.)

PRINCIPAL DUTIES AND RESPONSIBILITIES:

• Develop micro-architecture, design and program specific documentation
• Design and modelling of compute ASIC modules and sub-systems.
• RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals.
• Resolves architecture, design, or verification problems by applying sound ASIC engineering practices
• Use of various design tools (Synopsys, Compiler Linting, CDC, LEC, CLP etc.) to check and improve design quality
• Help the design verification team execute on the functional verification strategy.
• Generates innovative ideas for IP core and process flow improvements

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

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