Backend Engineer, Full Chip Layout

6 Months ago • 4-6 Years

Backend Development

Job Description

NVIDIA seeks experienced Backend Engineers for full-chip layout physical design. Responsibilities include full-chip layout implementation and analysis, resolving complex layout and congestion issues, and working with tools like Synopsys and Cadence. The role involves all aspects of layout implementation and analysis (DRC, LVS, ANT), targeting area, route, and integration within challenging constraints. The ideal candidate will have 4-6 years of experience as a BE/LO engineer, strong communication skills, and the ability to adapt to new technologies. The position offers the opportunity to work on high-cell count and high-speed designs, contributing to groundbreaking chip development within a dynamic and professional environment.

Good To Have:

Knowledge of PNR, STA, physical verification
Familiarity with Synopsys/Cadence tools

Must Have:

4-6 years BE/LO experience
Full chip layout implementation & analysis
DRC, LVS, ANT expertise
Problem-solving skills
Strong communication

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NVIDIA is looking for best-in-class full chip layout Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Full Chip Layout implementation and analysis of partition groups / top-level according to specifications, under challenging constraints, targeting for the area, route and integration.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex layout and congestion problems.
Daily work involves all aspects of layout implementation and analysis - DRC, LVS, ANT for partition groups and full chip level.
Taking part inflows development.

What we need to see:

B.SC. in Electrical Engineering/Computer Engineering.
4-6 years of experience as BE/LO engineer.
Ability to quickly adapt to new technology and go deep into new areas
Strong communication skills
Great teammate.
Drive new solutions based on any issues that arise

Ways to stand out from the crowd:

Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

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