Backend Physical Design Student

Join the Intel High Performance Processor (P-Core) team, contributing to the design of future-generation microprocessors. This role involves implementing high-performance block-level physical design from RTL to GDS, preparing design databases for manufacturing. You will conduct various aspects of the physical design flow, including synthesis, place and route, clock tree synthesis, and static timing analysis. Responsibilities also include verification and signoff processes, optimizing designs for power, frequency, and area, and participating in methodology development.

Must Have

• Student in computer engineering, electrical engineering, or computer science.
• At least 1.5 years until graduation.
• Availability of at least 40 hours a week.
• Ability to work in a dynamic and challenging environment.
• High learning ability.
• Ability to cope with several tasks simultaneously.

Good to Have

• Good level of English.

Perks & Benefits

• Hybrid work model

Job Description:

About the Team: We created the Intel High Performance Processor (P-Core), a disruptive technology that enables a broad range of devices from entry PCs to high end servers. You will be part of a team, participating in the design of a future generation of high performance Intel microprocessor. We offer a wide variety of roles. Among them. Perform implementation of High-performance block level physical design from RTL to GDS to create a design database that is ready for manufacturing.Conduct all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conduct verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Achieving final convergence. Possess expertise in various aspects of structural and physical design, including physical Layout design ,physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools (Cadence/Synopsys/Mentor/Ansys).Optimize and converge design to meet and improve product-level parameters such as power, frequency, and area.Participate in the development and improvement of physical design methodologies and flow automation.

Qualifications:

Relevant education computer engineering students Or a student in electrical engineering or computer science at colleges At least 1.5 years till graduation Location of position Intel Haifa Matam Personal qualities Teamwork ability in a dynamic and challenging environment enables high learning ability to cope with several tasks at the same time teamwork ability serviceability dynamic work ability English at a good level an advantage Availability of at least 40 hours a week

Job Type: Student / Intern

Shift: Shift 1 (Israel)

Primary Location: Israel, Haifa

Additional Locations:

Business group: The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust: N/A

Work Model for this Role: This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.