Design Engineer II

2 Weeks ago • 3-6 Years
Software Development & Engineering

Job Description

As a Design Engineer II, you will be responsible for chip-level IO planning, bump planning, and RDL routing, coordinating with FCFP and Block Owners for RDL integration, and performing IP integration activities for components like PLL and PVT Sensors. The role requires 3-6 years of experience with strong hands-on skills in IO & RDL, IP DRC, LVS checks, and debugging LVS issues. A good understanding of Latch-up issues, soft checks, and PnR flow is essential, along with exposure to Cadence EDA tools.
Good To Have:
  • Complex IP hardening like DDR, PCIe, MiPi etc.
  • Idea on PG Mesh Structures and Track Optimizations
  • TCL and PERL scripting knowledge and experience in writing the scripts
  • Hands-on experience in low power designs
  • Exposure to any of 7/6nm, 5/4nm & 3/2nm technologies
Must Have:
  • Chip Level IO Planning
  • Bump Planning
  • RDL Routing
  • Coordination with FCFP and Block Owners for RDL integration
  • IP Integration activities for PLL, PVT Sensors etc.
  • 3+ years of experience in IO & RDL
  • Hands-on experience in IP DRC and LVS checks
  • Hands-on experience in IP Integrations
  • Good in debugging LVS issues related to IO Plan
  • Good understanding of Latch up issues, soft checks etc.
  • Understanding of PnR flow
  • Good exposure to Cadence EDA or any other tool set needed for IO & RDL

Add these skills to join the top 1% applicants for this job

problem-solving
game-texts
perl

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • Experience : 3 to 6 + Years
  • Qualification : BE or B.Tech / ME or M.Tech
  • Responsibilities
  • Chip Level IO Planning, Bump Planning and RDL Routing
  • Coordination with FCFP and Block Owners for the RDL integration
  • IP Integration activities for PLL, PVT Sensors etc
  • Required Skills
  • 3+ years of experience in IO & RDL
  • Handson experience in IP DRC and LVS checks and IP Integrations
  • Good in debugging the LVS issues related to IO Plan
  • Good understanding of Latch up issues, soft checks etc.
  • Understanding of PnR flow
  • Good exposure to Cadence EDA or any other tool set needed for IO & RDL
  • Optional Skills
  • Complex IP hardening like DDR, PCIe, MiPi etc.
  • Idea on PG Mesh Structures and Track Optimizations
  • TCL and PERL scripting knowledge and experience in writing the scripts
  • Hands on experience in low power designs
  • Exposure to any of 7/6nm, 5/4nm & 3/2nm technologies

We’re doing work that matters. Help us solve what others can’t.

About Us

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Set alerts for more jobs like Design Engineer II
Set alerts for new jobs by Cadence
Set alerts for new Software Development & Engineering jobs in India
Set alerts for new jobs in India
Set alerts for Software Development & Engineering (Remote) jobs
Contact Us
hello@outscal.com
Made in INDIA 💛💙