Digital IC design Engineer

Your Team, Your Impact

As a Hardware Design Senior Staff Engineer with Marvell, you’ll be a member of the Custom compute and solutions group.

Our design team works on state-of-the-art datacenter and AI SOCs. As a member of the R&D team, you will design world-class hardware for the

industry's largest customers.

This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are

often other chip companies and big tech companies, familiar names to all candidates.

What You Can Expect

In this role, you will:

• Define the micro-architecture of SoCs, including its blocks, cores, accelerators, and subsystems.
• Work closely with the architecture, floor planning, backend, verification, DFT, STA teams, and other cross-functional teams to produce high-quality hardware.
• Develop and write micro-architectural specifications of the design.
• Implement designs using good RTL coding and low power techniques.
• Collaborate with the backend team to close on synthesis, place and route, and timing signoff.
• Collaborate with the verification team on pre-silicon verification tasks such as reviewing test plans, coverage closure, and full-chip simulation debug.
• Plan, scope, and time tasks with the project manager.
• Work with post post-silicon group to resolve any lab issues and successfully bring up silicon.
• Collaborate with the software team to ensure customer use cases requirements are met.

What We're Looking For

• Bachelor’s degree in computer science, Electrical Engineering, or related fields, and 12+ years of related professional experience. Or a Master’s degree in computer science, Electrical Engineering, or related fields with 10+ years of experience. Or a PhD in Computer Science, Electrical Engineering, or related fields with 8+ years of experience.

To be successful in this role, you will need to be:

• Fluent in System Verilog RTL coding techniques.
• Familiar with modern SoC architectures and various interface technologies such as AXI, HBM, Ethernet, PCIe, and D2D.
• Experience in micro-architecture of complex custom/ASIC products, focusing in one or more of the following areas: NPU, embedded processors, DSP, graphics, and general-purpose microprocessors.
• RTL design experience, synthesis, static-timing closure, formal verification, gate-level simulations, and block-level functional verification.
• Experience in implementation/timing closure for high-speed design.
• Hands-on experience for all aspects of the chip-development process, with proficiency in front-end design tools and methodologies, is a plus.
• Experience in designing high-speed (>1 GHz)/high-performance embedded processor SOC products is a plus.
• Knowledge of scripting languages such as Python, Perl, Tcl, and UNIX shell is desirable.

Expected Base Pay Range (USD)

121,400 - 181,800, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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