Emulation (FPGA Design) Engineer / Bluetooth - Staff

4 Months ago • 8-12 Years

Software Development & Engineering

Job Description

As an Emulation (FPGA Design) Engineer, you will join a team designing IP and wireless sub-systems for market-leading products. You will be responsible for validating next-generation Bluetooth and other PAN IPs on emulation platforms. Your responsibilities include adapting designs for FPGA, defining constraints, running synthesis, floor planning, and generating bit files. You will collaborate with validation and firmware engineers, instrumenting test structures for debugging using various lab equipment. You will be working on next-generation Wireless PAN technologies (Bluetooth, UWB, Thread, etc.) for connectivity solutions within mobile phones, wearables, IOT and Voice & Music chips.

Good To Have:

Exposure to Bluetooth/BLE Technologies.
Exposure to scripting languages like Perl and/or Python

Must Have:

8-12 years of experience in FPGA design implementation.
Expertise in RTL coding using Verilog/SV for complex designs.
Expertise in all aspects of FPGA design: constraint definition etc.
Proficiency with FPGA EDA tools: Synplify, Vivado, ISE, Chipscope.
Knowledge of latest FPGA architectures and partitioning designs.
Strong debugging, analytical and communication skills.

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communication

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Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Job Function

You would be joining a team with deep expertise in designing IP and wireless sub-systems for market leading products. You would work on cutting edge next-generation Wireless PAN technologies (Bluetooth, UWB, Thread, etc.) for connectivity solutions within mobile phones, wearables, IOT and Voice & Music chips.

In this role you will be working with the IP designers, Verification engineers, Validation engineers, Firmware and SoC engineers to validate the next generation Bluetooth and other PAN IPs on Qualcomm proprietary as well as industry standard emulation platforms. You will be responsible for taking the IP through the entire FPGA design implementation cycle. You will code the necessary emulation specific RTL needed to exercise the IP. You will be directly responsible for adapting the design for FPGA, come up with the timing constraints, run synthesis, floorplan the design for the target FPGA, run place & route tools and generate bit files. You will work closely with validation and Firmware engineers to instrument test structures for observing and logging signals during debug using ILA/Chipscope, Logic Analyzer, Oscilloscope and other lab equipment.

Skills/Experience

8-12 years of hands-on experience in implementing designs on FPGA
Strong expertise in RTL coding of complex designs using Verilog/SV
Expertise in all aspects of FPGA design; constraint definition, synthesis, floor planning, P&R, Timing closure, bitfile generation
Strong proficiency with FPGA EDA tools: Synplify, Vivado, ISE, Chipscope
Knowledge of the latest FPGA architectures and partitioning designs across multiple FPGAs
Exposure to scripting languages
Familiarity with lab equipment
Familiarity with interface protocols desired
Strong debugging, analytical and written/oral communication skills

Minimum Qualifications

Bachelor’s or Master’s Degree in Engineering in Electronics, VLSI, Communications or related field
8 years of industry experience in Digital Design

Preferred Qualifications

Exposure to Bluetooth/BLE Technologies and scripting languages like Perl and/or Python

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

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