Infra- Staff Design Verification Engineer

13 Hours ago • 1 Years +

Testing

Job Description

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation. This Hardware Engineer role involves planning, designing, optimizing, verifying, and testing electronic systems. Key responsibilities include developing and maintaining UVM-based verification environments for high-speed interconnect protocols (PCIe, CXL, AXI), creating and executing verification plans, performing block-level and top-level verification, and collaborating with cross-functional teams to ensure design correctness and coverage closure. The role also involves integrating SMMU and Coresight components, driving verification closure, and contributing to performance, power, and cost optimization.

Good To Have:

Bachelor’s/Master’s/Ph.D. in Electrical, Electronics, or Computer Engineering.
8+ years of ASIC/Subsystem/SoC verification experience.
Experience with PCIe, USB, Ethernet, or other peripheral protocols.
Exposure to post-silicon validation and lab bring-up.

Must Have:

Develop and maintain UVM-based verification environments for high-speed interconnect protocols (PCIe, CXL, AXI).
Create and execute verification plans for high-speed interconnect protocols including PCIe, CXL, AXI, and CHI.
Perform block-level and top-level verification, including functional coverage, assertion-based verification, and regression testing.
Collaborate with RTL designers, architects, and validation teams to ensure design correctness and coverage closure.
Work closely with design and architecture teams to understand specifications and derive verification strategies.
Use third-party VIPs (e.g., Synopsys, Mentor) for protocol compliance and simulation.
Implement and enhance scoreboards, agents, monitors, and sequences.
Integrate and validate SMMU and Coresight components in Subsystem environments.
Drive verification closure through coverage convergence and assertion-based verification.
Contribute to performance, power, and cost optimization considerations during verification.
Mentor junior engineers and contribute to verification methodology improvements.
Debug failures at RTL and gate-level simulations.
Strong proficiency in System Verilog, UVM, and verification methodologies.
Deep understanding of PCIe Gen3/Gen4/Gen5/Gen6, CXL 1.1/2.0/3.0, AXI/CHI protocols, and SMMU/Coresight architecture.
Expertise in assertion-based verification (SVA) and coverage-driven testing.
Proficiency in Perl/Python/Tcl scripting for automation.
Knowledge of power-aware verification (UPF), formal verification, and performance/power optimization.
Experience with coverage-driven verification and random constraint-based testing.

Perks:

World-class health benefit options providing world-class coverage to employees and their eligible dependents.
Programs designed to help employees build and prepare for a financially secure future.
Self and family resources to build emotional/mental strength and resilience, and define purpose.
Wellbeing programs and resources to help employees Live+Well and Work+Well.
Continuous learning and development programs.
Tuition reimbursement.
Mentorships.

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Job Posting Date

2025-10-22

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Key Responsibilities:

Develop and maintain UVM-based verification environments for high-speed interconnect protocols (PCIe, CXL, AXI).
Create and execute verification plans for high-speed interconnect protocols including PCIe, CXL, AXI, and CHI.
Perform block-level and top-level verification, including functional coverage, assertion-based verification, and regression testing.
Collaborate with RTL designers, architects, and validation teams to ensure design correctness and coverage closure.
Work closely with design and architecture teams to understand specifications and derive verification strategies.
Use third-party VIPs (e.g., Synopsys, Mentor) for protocol compliance and simulation.
Implement and enhance scoreboards, agents, monitors, and sequences.
Integrate and validate SMMU and Coresight components in Subsystem environments.
Drive verification closure through coverage convergence and assertion-based verification.
Contribute to performance, power, and cost optimization considerations during verification.
Mentor junior engineers and contribute to verification methodology improvements.
Debug failures at RTL and gate-level simulations.

Required Skills:

Strong proficiency in System Verilog, UVM, and verification methodologies.
Deep understanding of PCIe Gen3/Gen4/Gen5/Gen6, CXL 1.1/2.0/3.0, AXI/CHI protocols, and SMMU/Coresight architecture.
Familiarity with Synopsys/Mentor VIPs for PCIe/CXL and AMBA protocols.
Expertise in assertion-based verification (SVA) and coverage-driven testing.
Proficiency in Perl/Python/Tcl scripting for automation.
Knowledge of power-aware verification (UPF), formal verification, and performance/power optimization.
Experience with coverage-driven verification and random constraint-based testing.
Experience with scripting languages like Python, Perl, or Tcl.

Preferred Qualifications: