Lead Application Engineer-Analog Design

8 Minutes ago • 5 Years +

Design

Job Description

Cadence is seeking a Lead Application Engineer for Analog Design to provide customer support and consulting for its A/MS IC design environment, specifically the Virtuoso platform, including Virtuoso Schematic Editor and Spectre Circuit Simulator. The role requires at least 5 years of experience in A/MS IC circuit design, proficiency in various simulations and analyses, programming skills, and strong communication abilities in both English and Japanese.

Good To Have:

English or Chinese communication skill is a plus.
Verilog-A/Verilog-AMS/System Verilog Real modeling experience is a plus.
Knowledge of 16nm (or beyond) process desirable.
Over 3 years of experience for A/MS design or product support as CAD engineer.
Experiences on Virtuoso or Spectre desirable.

Must Have:

Provide customer support/consulting based on Virtuoso platform, Cadence's A/MS IC design environment.
Knowledge of Virtuoso Schematic Editor (VSE) and Spectre Circuit Simulator.
At least 5 years of experience for A/MS IC circuit design and knowledge.
Experience with SPICE simulation / mixed-signal simulation.
Experience with signal integrity/power integrity analysis.
Experience with electromigration / IR drop analysis.
Experience with design rule/LVS(Layout vs Schematic)/parasitic extraction.
Knowledge and experience of thermal analysis for IC design/PCB/package.
Programming experiences, such as Perl, Tcl, Python, SKILL etc.
Good organization and communication skills between difference groups and customers.
Communication skill and technical conversation in English.
Must have Japanese communication skill.

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Customer support/consulting based on Virtuoso platform, Cadence's A/MS IC design environment.
Main product：Virtuoso Schematic Editor (VSE), Spectre Circuit Simulator
https://www.cadence.com/en_US/home/tools/custom-ic-analog-rf-design/circuit-design.html

Qualification Requirements

Majored in Electrical Engineering or some other equivalent
Has the knowledge and desire to take on new challenges

Experiences/Skills

At least 5 years of experience for A/MS IC circuit design and knowledge.
Having experiences of SPICE simulation / mixed-signal simulation.
Having experiences of signal integrity/power integrity analysis.
Having experiences of electromigration / IR drop analysis.
Having experiences of design rule/LVS(Layout vs Schematic)/parasitic extraction.
Having knowledge and experience of thermal analysis for IC design/PCB/package.
Programing experiences, such as Perl, Tcl, Python, SKILL etc.
Good organization and communication skills between difference groups and customers.
Communication skill and technical conversation in English.
Must have Japanese communication skill. English or Chinese is a plus.
Verilog-A/Verilog-AMS/System Verilog Real modeling experience is a plus.
Knowledge of 16nm (or beyond) process desirable.
Over 3 years of experience for A/MS design or product support as CAD engineer. Experiences on Virtuoso or Spectre desirable

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