Member of Technical Staff
Job Description
- Comprehend high-level chip architecture
- Create full system simulation models in simulators like gem5
- Characterize micro-architecture details and leverage performance data
- Guide and optimize hardware design
- Craft, verify and debug performance test plans for hardware blocks (IO adapter unit, IOMMU, Ethernet)
- Ensure key design metrics such as bandwidth and latency are achieved
- Develop efficient performance debug tools to monitor system’s performance
- Collect over-time data for post-run analysis
- Work with architects to analyze performance stats and run system-level benchmarks
- Define future architectures of the products
- Propose, define and lead investigations of new performance features
- Improve the system’s overall efficiency
Comprehend the high-level chip architecture, create full system simulation models in simulators like gem5 to characterize the micro-arch details, and leverage performance data to guide and optimize the hardware design. Craft, verify and debug performance test plans for different hardware blocks, including IO adapter unit, IOMMU and Ethernet to ensure key design metrics such as bandwidth and latency are properly achieved. Develop efficient performance debug tools to monitor system’s performance in different testing scenarios and collect over-time data for post-run analysis. Work with architects to analyze performance stats and run system-level benchmarks to define the future architectures of the products. Propose, define and lead the investigations of new performance features which are aimed at improving the system’s overall efficiency.
Education
- Bachelor’s or foreign equivalent in Electrical Engineering, Computer Engineering, or related field
Experience
- 1 year of experience in job offered or related occupation.
Special Requirements: Must have at least 1 year of prior work experience in each of the following:
- 1. Verifying pre-silicon ASIC design, architecture, and golden models of different SoC units using Emulation and Prototyping platforms from Cadence and Synopsys.
- 2. Working with different hardware and software teams to execute and debug test plans spanning CPU, GPU and SoC levels, and to boot up and verify kernel images on Emulators for thorough pre-silicon validation.
- 3. Automating emulation flow and developing customized debug interfaces with Python, C and TCL.
