Mixed-Signal Model Verification Engineer

As a Mixed-Signal Model Verification Engineer, your primary responsibility will be to verify mixed-signal behavioral models created using SystemVerilog. This involves developing self-checking testbenches to simulate the models against the circuits they represent, ensuring their accuracy. You will conduct functional testing against the specifications and create assertions to identify illegal operating conditions. Furthermore, you will assist in setting up and executing static flows such as formal logical equivalence, linting, and timing checks. Your contributions will be crucial in streamlining and automating these flows across mixed-signal design teams. The goal is to ensure the models function correctly and efficiently within the larger design process.

Must Have

• Verifying mixed-signal behavioral models
• Creating self-checking testbenches in SystemVerilog
• Functional testing against specifications
• Creating assertions to flag illegal operating conditions
• Setting up and running static flows (formal, linting, timing)