PD/STA Engineer, Staff
Job Description
- Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling
- Hands-on experience with STA tools - Prime-time, Tempus
- Experience in driving timing convergence at Chip-level and Hard-Macro level
- In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling
- Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)
- Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation
- Proficient in scripting languages – TCL, Perl, Awk
- Basic knowledge of device physics
- STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs
- Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus
- Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation
- Evaluate multiple timing methodologies/tools on different designs and technology nodes
- Work on automation scripts within STA/PD tools for methodology development
- Experience in design automation using TCL/Perl/Python
- Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus
- Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field and 3+ years of Hardware Engineering or related work experience
- World-class health benefit option providing world-class coverage to employees and their eligible dependents
- Programs designed to help employees build and prepare for a financially secure future
- Self and family resources to build emotional/mental strength and resilience, as well as define purpose
- Wellbeing programs and resources to help employees Live+Well and Work+Well
- Continuous learning and development programs
- Tuition reimbursement
- Mentorships
Job Posting Date
2025-11-03
Job Area:
Engineering Group, Engineering Group > Hardware Engineering
General Summary:
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
Responsibilities:
- STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.
- Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
- Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
- Evaluate multiple timing methodologies/tools on different designs and technology nodes.
- Work on automation scripts within STA/PD tools for methodology development.
- Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment
- Experience in design automation using TCL/Perl/Python.
- Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus
- Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.
Education : B.Tech or MTech/MS in Electrical/Electronics/Microelectronics/VLSI.
Preferred Qualification/Skills
5+ years
- Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling
- Hands-on experience with STA tools - Prime-time, Tempus
- Have experience in driving timing convergence at Chip-level and Hard-Macro level
- In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,
- Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)
- Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.
- Proficient is scripting languages – TCL, Perl, Awk
Basic knowledge of device physics
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