Physical Design Power Optimization Engineer

NVIDIA is seeking a Physical Design Power Optimization Engineer to join the Networking Silicon Power engineering team. The role involves optimizing physical design for blocks/top-level/fc under challenging constraints, covering all aspects of chip development from RTL2GDS, including synthesis, power and clock distribution, place and route, timing closure, and power/noise fixes. Responsibilities also include power estimation and modeling. The ideal candidate will have 2+ years of experience in physical design and/or backend power optimization, with familiarity with EDA tools like Synopsys and Cadence.

Must Have

• Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.
• Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
• Power estimation and power modeling.
• B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering.
• 2+ years of experience in physical design and/or BE power optimization aspects.
• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
• Excellent problem-solving, partnership, and interpersonal skills.

Good to Have

• Knowledge in physical design flows and methodologies (PNR, STA, physical verification) is an advantage.
• FE design experience is an advantage.

NVIDIA is looking for best-in-class Physical Design Power Engineer to join our outstanding Networking Silicon Power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best Power! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

• Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.
• Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
• Power estimation and power modeling.

What we need to see:

• B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering.
• 2+ years of experience in physical design and/or BE power optimization aspects.
• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
• Knowledge in physical design flows and methodologies (PNR, STA, physical verification) is an advantage.
• FE design experience is an advantage.
• Excellent problem-solving, partnership, and interpersonal skills.

NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!