Pre-Si Verification Lead/Engineer

1 Minute ago • 7 Years + • Software Development & Engineering

Job Summary

Job Description

The Client Development Group Bangalore, India is seeking a highly motivated SOC Pre-Si Verification Lead for the next generation of Client SOC. Responsibilities include owning or leading verification of complex flows at SOC, subsystem, or IP levels, defining verification strategies and test plans, developing verification environments, and debugging simulations. The role involves applying random-stimulus and coverage-based techniques, innovating for efficiency, and mentoring teams. Candidates should have 7+ years in design verification, experience with multiple product cycles, and expertise in SV-UVM and RTL debugging.
Must have:
  • Own or lead verification of complex flows at SOC, subsystem, or IP levels
  • Define verification strategies and test plans
  • Develop verification environments
  • Run and debug simulations
  • Apply random-stimulus and coverage-based techniques
  • Plan verification of complex design IP/SS/SoC
  • 7+ years of experience in design verification
  • Experience with verification for multiple product cycles
  • Expertise in writing test plans, developing tests, debugging failures, and coverage signoff in SV-UVM
  • Substantial background in debugging RTL (Verilog) designs
  • Experience with simulation and/or emulation environments
Good to have:
  • Knowledge in SoC high-speed IO protocols, Fabric-NOC, MemSS, Graphics, Multimedia, Coherency cluster integration and System level flows verification
  • Hands-on experience with formal verification
  • Experience of working on x86 arch based High performing/Low Power SoCs
  • Scripting language such as Python or Perl

Job Details

Job Description:

  • The Client Development Group Bangalore, India is looking for a highly motivated SOC Pre-Si Verification Lead to join the compute die frontend DV team for the next generation of Client SOC.
  • ResponsibilitiesOwn or lead verification of complex flows at the SOC, subsystem, or IP levelsLearn about the design and interact with partner teams to define verification strategies and test plans.
  • Develop verification environments and run and debug simulations to drive quality.
  • Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals.
  • Innovate to improve verification efficiency through methodologies or tools Coach and mentor team in your areas of expertise.
  • Demonstrate core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity and Inclusion.
  • Plan the verification of complex design IP/SS/SoC interacting with the architecture and design engineers to identify verification test scenarios.
  • Facilitate interactions with cross functional engineering organizations in supporting Project execution.
  • Project planning and scheduling of activities of local team and present and report progress on a regular basis.
  • Develop strategies, provide guidance and support team in addressing failure events.Formal : Good to have hands-on experience with formal verification .

Qualifications:

  • 7+ years of experience in design verification with a proven track record of delivering complex CPU or SoC IP's/SS.
  • Experience with verification for multiple product cycles from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff in SV-UVM.
  • Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
  • Desirable
  • Knowledge in SoC high-speed IO protocols, Fabric-NOC, MemSS, Graphics, Multimedia, Coherency cluster integration and System level flows verification.
  • Hands-on experience with formal verification.
  • Experience of working on x86 arch based High performing/Low Power SoCs.
  • Scripting language such as Python or Perl.

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