Principal Engineer, Device Modeling

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What You’ll Do

We are looking for experienced technologists who will independently research and explore future logic technology paths, capabilities, and applications through design/system-technology optimization.

The candidate will be a key technical member of the Logic Pathfinding Lab, part of the Samsung Semiconductor Inc (SSI) in San Jose.  He or she will join a team of experts in researching and evaluating advanced technology options, and assisting in knowledge / technology transfer to the Samsung Logic Technology Development (TD) in Korea. The successful candidate will be responsible for researching and evaluating new device architectures, materials, and integration schemes through chip design metrics to meet the need of sub-3nm technology nodes. 

The candidate should have strong background on block level PPA analysis and standard cell library generation. The candidate should have excellent communication skills, and be able to collaborate with and guide multiple organizations, including research consortia, to develop internal benchmarking needed in developing a technology roadmap.

Location: Working onsite at our San Jose headquarters at least 5 days per week.

Job ID: 42549

• Develop and analyze new CMOS and beyond-CMOS device architectures, including the required materials and integrations schemes.
• Develop internal benchmarking capability based on available data, modeling, and/or learnings from multiple sources, and create assessments to share with internal R&D team.
• Develop realistic device-level PPAC (power, performance, area, and cost) analysis for new technology options.

What You Bring

• PhD in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science and Engineering or related fields, and 15+ years of industry experience.
• Conceptualize, design, and assess new CMOS device architectures and logic structures involving new device materials, and process integration.
• Hands-on experience and understanding of the benefits and limitations of EDA tools in device and process modeling.
• Expertise in applying Machine Learning algorithms and approaches to accelerate and improve effectiveness of TCAD modeling.
• Deep knowledge of device physics for 3D logic structures, including emerging beyond-CMOS devices.
• Develop speculative integration flows and process assumptions, and assess risks.
• Deep understanding of requirements and design windows for applications including low-power, high-performance, embedded memory.
• Expertise in design and optimizations of advanced logic and memory standard cells.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

PREFERRED SKILLS

• Demonstrated experience and expertise in developing new CMOS device architectures.
• Understanding of FEOL, MOL, and BEOL process flows.
• Experience in designing logic test structures and using process emulators.
• Experience in device reliability assessment.
• Experience in guiding research consortia funded by the semiconductor industry and / or academic research in the field of device exploration.

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