RTL Design Engineer

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a results-oriented and outstandingly hardworking RTL Design Engineer. Are early in your journey towards a chip design career and wish to challenge yourself in a technical and multi-disciplinary effort, we have an exciting position for you in the world class Apple mixed-signal silicon design team. This position will encourage building of a solid foundation in logic circuits and gentle entry into understanding analog circuits. You will gain transparency into a variety of flows fundamental to modern silicon engineering: insight into full custom schematics for analog as well as high-speed digital circuits, translating functionality of such circuits into an efficient software behavioral representation, simulation of such code and ensuring formal equivalence between custom designs and their abstract representation. You will gain experience and knowledge into software methods and analysis that is increasingly important for a variety of disciplines. As a member of our wide-ranging group, you will have the outstanding and phenomenal opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. Your role will equip you with learning to specify, design, and help in the verification and lab bring-up of sophisticated mixed-signal circuits (digital side).

In this job you will get the opportunity to gain knowledge in designing micro-architecting digital blocks within sophisticated mixed-signal circuits. You will be also responsible for RTL coding of blocks specified by you or others. You will participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will participate in the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, etc.

• BS degree in technical discipline with minimum 3 years of relevant experience.

• Solid understanding of mixed signal concepts, RTL design, Verilog and SystemVerilog
• Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
• Validated knowledge of synthesis, static timing, DFT, is a plus
• Validated knowledge of SystemVerilog assertions, checkers, and other design verification techniques are a plus
• Knowledge of scripting languages. Perl and Python are plusses
• Strong communication and presentation skills