RTL Design Engineer-Staff(DDR)

Qualcomm India Private Limited is seeking an RTL Design Engineer-Staff (DDR) with 7+ years of ASIC design experience. Responsibilities include micro-architecture and RTL development, validation, working with verification teams, constraint development, timing closure, UPF writing, power-aware checks, and supporting integration and debug. The role requires expertise in multi-clock designs, asynchronous interfaces, and low-power SoC design.

Must Have

• MTech/BTech in EE/CS with 7+ years of ASIC design experience
• Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA
• Hands on experience in Multi Clock designs, Asynchronous interface
• Hands on experience in Low power SoC design
• Mirco architecture & RTL development and its validation for linting, clock-domain crossing and DFT rules
• Work with functional verification team on test-plan development and waveform debugs at core, sub-system, SoCs levels
• Hands on experience in constraint development and timing closure
• UPF writing, power aware equivalence checks and low power checks

Good to Have

• Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5/6)
• Understanding of protocols like AHB/AXI/ACE/CHI
• Experience with post-silicon bring-up and debug
• Able to work with teams across the globe and possess good communication skills

Perks & Benefits

• World-class health benefit option providing world-class coverage to employees and their eligible dependents
• Programs designed to help employees build and prepare for a financially secure future
• Self and family resources to build emotional/mental strength and resilience, and define purpose
• Wellbeing programs and resources to help employees Live+Well and Work+Well
• Continuous learning and development programs
• Tuition reimbursement
• Mentorships

General Summary:

Skills & Experience

• MTech/BTech in EE/CS with 7+ years of ASIC design experience.
• Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA
• Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5/6) is added advantage.
• Understanding of protocols like AHB/AXI/ACE/CHI is desirable.
• Experience with post-silicon bring-up and debug is a plus.
• Able to work with teams across the globe and possess good communication skills.
• Hands on experience in Multi Clock designs, Asynchronous interface is a must.
• Hands on experience in Low power SoC design is required.

Responsibilities

• Mirco architecture & RTL development and its validation for linting, clock-domain crossing and DFT rules.
• Work with functional verification team on test-plan development and waveform debugs at core, sub-system, SoCs levels.
• Hands on experience in constraint development and timing closure.
• UPF writing, power aware equivalence checks and low power checks.
• Support performance debugs and address performance bottle necks.
• Provide support to sub-system, SoC integration and chip level debug.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.