Senior Design Verification Engineer – AI and Video Processor IP

Qualcomm is seeking an ASIC verification engineer to develop world-class solutions for next-generation AI/ML and video processing IP. This role involves verifying and modeling multimedia and compute ASIC modules, creating comprehensive verification plans, developing reusable testbench components using SystemVerilog/UVM and C/C++, and optimizing coverage and test platform delivery processes. The engineer will also implement verification methodology and automation using scripting languages like Python and Perl, and develop performance verification monitors and test scenarios.

Must Have

• Verify features and performance of IP-level RTL using coverage-driven, constrained-random methodologies in System Verilog (UVM/OVM).
• Create comprehensive verification plans to describe the functional/feature test points of the DUT.
• Develop reusable testbench components such as scoreboards, reference models, checkers, drivers, monitors, and VIPs using SystemVerilog/UVM and C/C++.
• Create functional coverage models to track the IP verification quality relative to the DV plan.
• Develop SVA assertions for functional and formal verification.
• Implement verification methodology and automation using scripts (e.g. Python, Perl).
• Develop and support a regression and coverage flow to ensure high DV quality.
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Good to Have

• 2+ years in ASIC design verification.
• Proven experience verifying Verilog and/or System Verilog RTL designs.
• Working experience using testbench components such as Interface VIPs, reference models, scoreboards, transactors.
• Experience with functional model development (UVM, SystemC, SVAs, and/or C++).
• Experience with simulation and code coverage tools (VCS, Verdi, Modeltech/Questa, or Xcelium).
• Experience with design rule and Multi-frequency and CDC verification (SVA assertions).
• Experience with bus implementation/verification techniques.
• Experience with verification automation using Python, PERL, or other scripting languages.
• Practiced verification of data and/or image processing pipelines.
• Practiced verification of cache controllers.
• Practiced verification of clock domain crossing and Reset architecture.
• Practiced verification of bus interface protocols (APB, AHB, AXI) and RTL.
• Practiced verification of FIFOs and memory controllers.

Perks & Benefits

• World-class health benefit option providing world-class coverage to employees and their eligible dependents.
• Programs designed to help employees build and prepare for a financially secure future.
• Self and family resources to help build emotional/mental strength and resilience, as well as define purpose.
• Wellbeing programs and resources to support employees to Live+Well and Work+Well.
• Continuous learning and development programs.
• Tuition reimbursement.
• Mentorships.

Job Posting Date

2025-12-29

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Qualcomm enables a world where everyone and everything can be intelligently connected. As the world's leading wireless tech innovator, we push the boundaries of what's possible to enable next-gen experiences and drive digital transformation to help create a smarter, connected future for all. Our roadmap of breakthrough technologies expands our mobile innovations and solutions to support virtually every connected device. With our leadership in wireless connectivity, high-performance, low-power computing, and on-device AI, we’re powering the connected intelligent edge.

We are searching for an ASIC verification engineer interested in developing world-class solutions for the next generation of AI/ML and video processing IP.

This is New Position.

Principal Duties

• Verification and modelling of multimedia and compute ASIC modules and sub-systems
• Verify features and performance of IP-level RTL using coverage-driven, constrained-random methodologies in System Verilog (i.e. UVM/OVM)
• Create comprehensive verification plans to describe the functional/feature test points of the DUT, and present the plan to the IP team
• Develop reusable testbench components such as scoreboards, reference models, checkers, drivers, monitors, and VIPs using SystemVerilog/UVM and C/C++
• Create functional coverage models to track the IP verification quality relative to the DV plan
• Develop SVA assertions for functional and formal verification
• Optimize coverage and test platform delivery processes using AI toolsets
• Implement verification methodology and automation using scripts (e.g. Python, Perl)
• Create performance verification monitors, models, and test scenarios
• Develop and support a regression and coverage flow to ensure high DV quality

Preferred Qualifications:

• 2+ years in ASIC design verification
• Proven experience verifying Verilog and/or System Verilog RTL designs
• Working experience using testbench components such as Interface VIPs, reference models, scoreboards, transactors
• Experience with several of the following tools/techniques
• Functional model development (UVM, SystemC, SVAs, and/or C++)
• Simulation and code coverage tools (VCS, Verdi, Modeltech/Questa, or Xcelium)
• Design rule and Multi-frequency and CDC verification (SVA assertions)
• Bus implementation/verification techniques
• Verification automation using Python, PERL, or other scripting languages
• Practiced verification of one or more of the following
• Data and/or image processing pipelines
• Cache controllers
• Clock domain crossing and Reset architecture
• Bus interface protocols (APB, AHB, AXI) and RTL
• FIFOs and memory controllers

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field.