Senior Engineer, Physical Design

Marvell is seeking a Senior Engineer, Physical Design to join their team working on custom Processor/ASIC solutions. This role involves hands-on physical design of complex chips and methodology development for next-generation, high-performance processor chips in leading-edge CMOS process technology. Responsibilities include triaging workflows, running RTL code through synthesis and place and route tools, analyzing performance, verifying power grids, and reviewing sign-off checks for errors or optimizations. The position is full-time and on-site in Morrisville, NC or Burlington, VT.

Must Have

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields, or equivalent work experience
• Experience in physical design with a focus on block-level PNR for advanced CMOS process nodes (e.g., 7nm, 5nm, or below)
• Working experience with industry-standard EDA tools for physical design, including Cadence Genus and Innovus, and Synopsys Design Compiler, IC Compiler and Fusion Compiler
• Ability to work full-time, on-site at a designated team location

Good to Have

• Working knowledge of static timing analysis tools such as Tempus or PrimeTime
• Working knowledge of EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail
• Working knowledge of physical verification and formal verification tools (e.g., Calibre, LEC, Formality)

Perks & Benefits

• Flexible time off
• 401k
• Year-end shutdown
• Floating holidays
• Paid time off to volunteer

Your Team, Your Impact

Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications.

What You Can Expect

You will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. Every day, you’ll be working hands-on to triage workflows, whether you’re running RTL code through synthesis and place and route (PnR) tools to create the physical view of the chip, analyzing performance by running timing analysis, verifying a robust power grid by performing EMIR analysis, etc. There are many sign-off checks that need to happen to verify that the database is ready to move on to the next level, and it’s your responsibility to review completed runs for errors or create optimizations from successful runs.

We are hiring for multiple office locations. This is a full-time, on-site role, and employees are expected to work at their designated team location. Relocation assistance is available for qualified candidates.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields, or the equivalent work experience that provides knowledge and exposure to theories, principles and concepts
• Experience in physical design with a focus on block-level PNR for advanced CMOS process nodes (e.g., 7nm, 5nm, or below)
• Working experience with industry-standard EDA tools for physical design, including Cadence Genus and Innovus, and Synopsys Design Compier, IC Compiler and Fusion Compiler
• Working knowledge of static timing analysis tools such as Tempus or PrimeTime and EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail is advantageous
• Working knowledge of physical verification and formal verification tools (e.g., Calibre, LEC, Formality) is advantageous
• Enjoy learning by doing the work and having access to guides and a mentor
• Be willing to raise your hand and volunteer for learning opportunities you may not have experienced before

Expected Base Pay Range (USD)

90,400 - 133,760, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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