Senior Staff Design Verification Engineer
Job Description
- Architect and develop a functional verification environment, including reference models and bus-functional monitors and drivers.
- Contribute to the methodology behind functional verification environment development.
- Write a verification test plan that employs random techniques, directed testing and coverage analysis.
- Develop a testbench using UVM, System Verilog, C/C++, and DPI.
- Perform verification at different levels of hierarchy including block/unit, subsystem, and SOC levels.
- Work closely with logic designers to ensure test plan is complete, debug simulation failures, and resolve issues.
- BS/MS/PhD in Computer Science, Electrical Engineering, or Computer Engineering.
- 5-10 years of relevant professional experience.
- Background in creating test plans and designing test bench architectures that are hierarchical, reusable and scalable.
- Background in SOC verification and test bench development using UVM and System Verilog, object oriented programming, and constrained random methods.
- Experience with EDA verification and debugging tools, scripting languages such as Python or Perl, and revision control systems.
- flexible time off
- 401k
- year-end shutdown
- floating holidays
- paid time off to volunteer
About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading-edge data processing silicon platforms for AI, accelerated computing, cloud data center, and telecom customers. The group focuses on delivering innovative technology in diverse fast-growing product lines that encompass high performance design, advanced die-to-die and packaging technology, and optimized low-power techniques.
What You Can Expect
In this role, you will architect and develop a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development.
Activities may include:
- Writing a verification test plan that employs random techniques, directed testing and coverage analysis to thoroughly check functional correctness and performance.
- Developing a testbench using UVM, System Verilog, C/C++, and DPI.
- Verification at different levels of hierarchy including block/unit, subsystem, and SOC levels.
- Working closely with logic designers to ensure the test plan is complete, debug simulation failures, and resolve issues.
What We're Looking For
- BS/MS/PhD in Computer Science, Electrical Engineering, or Computer Engineering, 5-10 years of relevant professional experience.
- Background in creating test plans and designing test bench architectures that are hierarchical, reusable and scalable.
- Background in SOC verification and test bench development using UVM and System Verilog, object oriented programming, and constrained random methods.
- Experience with EDA verification and debugging tools, scripting languages such as Python or Perl, and revision control systems.
Other skills:
- Effective communication and teamwork skills
- Mindset for high quality and attention to detail
- Independent learner, proactive in problem solving and finding solutions
Expected Base Pay Range (USD)
124,420 - 186,400, $ per annum
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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