Senior Staff Verification Engineer

4 Months ago • 8 Years +

Job Summary

Job Description

This role involves working as a Senior Staff Verification Engineer at Enphase Energy, a global energy technology company. The engineer will be part of a team in Bangalore, India, focusing on verifying RISC-V based subsystems for ARM Cortex M4 based ASICs using System Verilog. Responsibilities include creating verification plans, building test benches, developing test cases, and ensuring the functional correctness of the Design Under Test (DUT). The engineer will also generate coverage metrics, collaborate with IP developers, and provide test vectors for post-silicon validation. The role demands strong problem-solving, and communication skills, along with experience in logic verification and a deep understanding of RISC-V architecture and processor toolchains.

Must have:

Proficient in UVM, Verilog, SystemVerilog, C, Python.
Strong understanding of logic verification environment (UVM & System Verilog)
Strong understanding of RISC-V architecture & functional verification
Experience with processor toolchains (compiler, assembler, simulator).
Experience with processor verification: directed/random tests.
Experience with functional processor simulators.

3 skills required

3 skills required for this role

Add these skills to join the top 1% applicants for this job

python

communication

test-coverage

Job Details

Enphase Energy is a global energy technology company and leading provider of solar, battery, and electric vehicle charging products. Founded in 2006, Enphase transformed the solar industry with our revolutionary microinverter technology, which turns sunlight into a safe, reliable, resilient, and scalable source of energy to power our lives. Today, the Enphase Energy System helps people make, use, save, and sell their own power. Enphase is also one of the fastest growing and innovative clean energy companies in the world, with approximately 68 million products installed across more than 145 countries.

We are building teams that are designing, developing, and manufacturing next-generation energy technologies and our work environment is fast-paced, fun and full of exciting new projects.

If you are passionate about advancing a more sustainable future, this is the perfect time to join Enphase!

About the role

Enphase is looking for mid-level engineer to join our team in Bangalore India with verification experience in System Verilog for RISC-V based subsystem to be used in our ARM Cortex M4 based ASICs. The team is working on development of our next generation Control ASIC to production in 22nm technology. The ASIC will be a Mixed Signal SOC built around ARM microcontrollers.

What you will do

Work on creating verification plan for RISC-V based application specific IP
Build Standalone IP test bench using System Verilog
Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC)
Use the IP/SOC RTL in system verilog based logic verification environment & complete the functional verification
Generate functional and code coverage metrics, collaborate with IP developers on the correctness & completeness of IP functionality.
Deliver the functional test vectors needed to be used for post-silicon validation.
Be the single point contact for the concerned IP Verification and enable the Tapeout for all control ASICs of Enphase

Who you are and what you bring

Proficient in UVM, Verilog, SystemVerilog, C, Python. Working on the HW/SW interface.
Strong understanding and experience of logic verification environment (UVM & System Verilog)
Strong understanding of RISC-V architecture & functional verification
Experience with processor toolchains (compiler, assembler, simulator).
Experience with processor verification. Directed tests and random program generated tests.
Experience with functional processor simulators.
Experience with verification of secure processor boot code.
Experience with Floating point instructions implementation & verification in micro controller based ASIC designs
Ability to quickly adapt to other categories of C-based/System Verilog based IP verification
Experience and ability to bring complex SOCs into the physical world and into production.
Excellent problem solving skills, written & verbal communication skills
#Logic Verification #Embedded C Verification #ARM #Boot.
Prior hands on work experience of at least 8 years in Logic IP Verification based on System Verilog.