SIPI & PMIC Engineer, Senior

2 Months ago • 2 Years +

Software Development & Engineering

Job Description

The Qualcomm Package Electrical Team is seeking a Senior SIPI & PMIC Engineer to optimize package design by collaborating with package and IC designers. Responsibilities include working with substrate designers to ensure system-level constraints are met before package Tape-out. The candidate will liaise with PHY owners to understand specifications for various IPs like PCIe, UFS, USB, MIPI, and LPDDR, and with PCB designers to evaluate the impact of Ball assignment on system-level performance. Additionally, the role involves working with the PMIC design lead to implement Power Integrity solutions for various PMICs. The position requires communication across multiple organizations including PHY, SoC, PMIC, and System PCB teams, providing timely feedback to stakeholders.

Good To Have:

Experience in modeling and analysis of Product Power supply solution.
Working knowledge in Cadence Allegro/APD/Sip or Mentor Xpedition.
Experience in programming language (C/C++) or scripting language (Perl/Python).
Experience in Matlab to automate simulation flow.

Must Have:

Perform package characterization and modeling for DDR, SerDes & Mixed signal.
Perform system-level analysis for DDR, SerDes & Mixed signal interfaces.
Perform Power Integrity simulations at Pre-layout and Post layout.
Analyze Power Delivery Network on Interposer and Substrate.
Provide design guidelines for Package design optimization.
Develop design & analysis flow and automate the process.
Experience in Electromagnetics and transmission line theory & Crosstalk.
Proficiency in field solvers (HFSS, Q3D, Sentinel-PSI, Clarity).
Experience in simulation tools (ADS and Hspice).

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Job Description

The Qualcomm Package Electrical Team has an opening in the areas of signal integrity and power integrity. The candidate will work with package and IC designers to find ways to optimize the overall package design. The candidate’s responsibility is working with substrate designers to make sure all system level constraints are met prior to the package Tape-out.

The candidate is expected to communicate with PHY owners to understand the Specs for various IPs such as PCIe, UFS, USB, MIPI, LPDDR, etc, and also with PCB designers to assess the impact of Ball assignment to the system level performance. The candidate will also work with PMIC design lead for executing Power integrity solutions for various PMICs.

This position offers the opportunity to work across multiple organizations such as PHY team, SoC team, PMIC team, System PCB team and providing timely feedback to the various steak-holders is essential.

The responsibilities will include but not be limited to the following:

Perform package characterization and modeling for DDR, SerDes & Mixed signal.
Ability to perform system-level analysis for DDR, SerDes & Mixed signal interfaces.
Perform Power Integrity simulations at Pre-layout and Post layout design phases.
Analyze Power Delivery Network on Interposer and Substrate.
Provide design guidelines for Package design optimization
Develop design & analysis flow and automate the process

Minimum Qualifications:

BS and a minimum of 2 years of relevant industry experience
Experience in Electromagnetics and solid background on transmission line theory & Crosstalk
Proficiency in field solvers such as HFSS, Q3D, Sentinel-PSI and Clarity
Experience in simulation tools such as ADS and Hspice

Preferred Qualifications:

MS with 3+ years of experience in DDR/SerDes in Package/PCB/System Design, but Ph.D with minimal experience is considered as well
Experience in modeling and analysis of Product Power supply solution including PKG, PCB & VRM.
Working knowledge in Cadence Allegro/APD/Sip or Mentor Xpedition
Experience in programming language(c/c++) or scripting language(Perl/Python) is a plus
Experience in Matlab to be able to automate existing simulation flow