Sr Application Engineer

This Sr Application Engineer role at Cadence involves collaborating with the sales team to identify and scope opportunities for functional logic verification platforms. The engineer will understand project goals, plan and execute technical evaluations with customers and colleagues, and report on tasks. Responsibilities also include training customers, providing technical expertise, and ramping up team members on advanced verification technologies. The role requires strong hands-on experience in hardware design and verification techniques, including HDL simulation and SystemVerilog/Verilog/VHDL/SystemC.

Must Have

• Work closely with the sales team to identify and scope opportunities for the Cadence functional logic verification platform
• Understand the Goal and Objective, then plan and execute and manage key technical evaluations by co-working proactively with existing and potential customers as well as team colleagues
• Summarize the tasks and projects, and report to manager and share with team effectively
• Train, ramp-up and accompany customer project
• Conduct basic and advanced trainings, presentations and demos as necessary
• Ramp-up other members of the team on the advanced verification technologies and tools
• Providing technical expertise to address clients’ queries, which need expert involvement
• Possess minimum BS level of CS or EE with 3+ years of industry experience
• Minimum 3+ years hands-on, high expertise on hardware design & verification techniques
• Hands on experience using HDL simulator (e.g. ies, vcs or questa)
• Hands on Verification experience using SystemVerilog/Verilog/VHDL/SystemC
• Hands-on Design experience using SystemVerilog, Verilog and VHDL
• Knowledge of VIPs, and code & functional coverage tools

Good to Have

• Experience on UVM methodology or similar one
• Knowledge of Metric Driven Verification (MDV) using vManager CS
• Hands-on experience optimizing RTL, Gate-level simulation for improving performance by using standard profiling tools
• Good communication skills in English and a strong desire for working in a global environment with customers and BU people
• Current passport is required with no travel limitations

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• Work closely with the sales team to identify and scope opportunities for the Cadence functional logic verification platform
• Understand the Goal and Objective, then plan and execute and manage key technical evaluations by co-working proactively with existing and potential customers as well as team colleagues
• Summarize the tasks and projects, and report to manager and share with team effectively
• Train, ramp-up and accompany customer project.
• Conduct basic and advanced trainings, presentations and demos as necessary.
• Ramp-up other members of the team on the advanced verification technologies and tools.
• Providing technical expertise to address clients’ queries, which need expert involvement

Requirement

• The candidate should possess minimum BS level of CS or EE with 3+ years of industry experience.
• Minimum 3+ years hands-on, high expertise on hardware design & verification techniques.
• Hands on experience using HDL simulator (e.g. ies, vcs or questa, but ies preferred) is a must.
• Hands on Verification experience using systemVerilog/Verilog/VHDL/SystemC.
• Experience on UVM methodology or similar one should be preferred.
• Hands-on Design experience using SystemVerilog, Verilog and VHDL. - Knowledge of VIPs, and code & functional coverage tools (IMC preferred) and technologies. - Knowledge of Metric Driven Verification (MDV) using vManager CS should be preferred.
• Hands-on experience optimizing RTL, Gate-level simulation for improving performance by using standard profiling tools is a big plus.
• Good communication skills in English and a strong desire for working in a global environment with customers and BU people.
• Current passport is required with no travel limitations

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