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Sr. CPU Architecture Verification Engineer

Karnataka, India (On-site)

Sr. CPU Architecture Verification Engineer

1 Month ago • 7 Years + • Research & Development

About the job

Summary

Seeking a Senior CPU Architecture Verification Engineer with 7+ years of experience in functional verification of CPU architectures. Must have strong knowledge of Verilog/SystemVerilog/C/C++/Assembly, ASIC design verification tools, and industry standard verification methodologies.

8 skills required for this role

Test your skills to join the top 1% applicants for this job

shell

cpp

python

perl

communication

scalability

networking

presentation-skills

Must have:

CPU Verification
ASIC Design
Verilog/SystemVerilog
Functional Verification

Good to have:

RISC-V
ARM
MIPS CPU
Multi-core Coherency

Perks:

Unlimited Growth
Industry Leading

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This position involves extensive hands-on experience with CPU verification using industry standard functional verification methodologies, formal verification and constrained random generators and reference model-based checkers. The candidate must be able to take critical decisions and completely own verification closure for a block or feature. This position involves cross functional interaction with CPU designers and architects and working across sites to ensure high quality CPU designs for customers.

Minimum Qualifications

Bachelors/Masters in Electronics/Electrical/Computer Engineering with 7+ years of industry experience with a focus on functional verification in CPU verification
Familiar with CPU architectures and superscalar designs and industry leading RISC processors
Exposure to various ASIC design verification tools with good digital design concepts
Knowledge and experince with Interconnect protocols like AXI/ACE/OCP/CHI
Scripting experience in Python/Perl/TCL/Shell
Experience in creating functional test plans and implementing them as part of pre-silicon verification
Strong knowledge of Verilog/SystemVerilog/C/C++/Assembly
Strong analytical and problem-solving skills
Self-motivated with excellent communication and presentation skills, and ability to collaborate well locally and with global team

Preferred Qualifications

Experience with RISC-V, ARM, and/or MIPS CPU
Experience with multi core and coherency in modern
Familiarity with functional safety flows and requirements

Here’s what you can expect from us:

At MIPS, you’ll be a member of a fast-growing team of technologists that are creating the industry’s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure – you’ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry’s most experienced CPU engineers. An unlimited growth path – with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers.

At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave!

More about us:

MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products.

Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.

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