Sr. Principal Design Engineer

Cadence Design Systems Inc. is seeking a motivated Sr. Principal Design Engineer in Belo Horizonte, Brazil. This role involves working with ASIC Design Verification flow, including daily activities related to Simulation DV, Emulation, and Post Silicon Bringup Validation. The ideal candidate will have strong expertise in building test-benches using System-Verilog, UVM, C/C++, and a solid understanding of digital logic fundamentals. Experience with functional/code coverage, SVA, and ASIC productization lifecycle is essential. Proficiency in scripting languages like Perl/Python and excellent communication skills are also required.

Must Have

• Complete Bachelor's degree in Electrical Engineering, Computer Science or related areas.
• Strong expertise in building test-benches using System-Verilog, UVM, C/C++.
• Strong digital logic fundamentals and understanding.
• Experience in functional coverage/code coverage/assertions (SVA) development and closure.
• Strong debug skills.
• Should have gone through complete lifecycle of ASIC productization.
• Proficient in scripting/automation using Perl / Python etc.
• Excellent verbal and written communication skills and a good team player.

Good to Have

• Experience in using emulation or post silicon desirable.

Perks & Benefits

• Competitive benefits.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Working at Cadence is very dynamic, fast-paced, and integrated with other teams all around the world.### Job Description:* Work with ASIC Design Verification flow.* Daily activities related with Simulation DV, Emulation, Post Silicion Bringup Validation.### Requirements:* Complete Bachelor's degree in Electrical Engineering, Computer Science or related areas.* Strong expertise in building test-benches using: System-Verilog, UVM, C/C++* Strong digital logic fundamentals and understanding* Experience in functional coverage/code coverage/assertions (SVA) development and closure* Strong debug skills* Should have gone through complete lifecycle of ASIC productization* Experience in using emulation or post silicon desirable but not mandatory* Proficient in scripting/automation using any standard scripting language like Perl / Python etc.* Excellent verbal and written communication skills and a good team player### Additional Job Details:* Employment category: CLT.* Employment term: 40 hours/week.* Competitive benefits.We’re doing work that matters. Help us solve what others can’t.