Sr Principal DFT Design Engineer

Cadence is seeking a Sr Principal DFT Design Engineer with 5-15 years of experience in SoC/ASIC Digital Design. The role requires expertise in scan chain insertion, compression scan technologies, MBIST, and ATPG. Responsibilities include systematic quality metrics driven ATPG pattern generation, verification, and debugging. The ideal candidate will possess strong problem-solving skills and the ability to work independently and collaboratively across cross-functional teams.

Must Have

• Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
• Intimate knowledge of DFT insertion flows
• Basic scan chain insertion using synthesis or other software tools
• Experience in compression scan insertion, LBIST and other scan technologies
• Intimate knowledge of memory built-in self-test (MBIST)
• Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
• Debug and Analysis of failures to improve fault coverage
• Verification of ATPG testbenches and debugging root cause of simulation mis-compares
• Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687
• Ability to work in collaborative team environment
• Should be able to finish DFT tasks independently
• Strong problem-solving skills, exhibit discipline, thoroughness, and methodical approach
• Ability to work with stakeholders across cross-functional teams
• Self-driven and committed individual who can work in a fast-paced project environment

Good to Have

• Knowledge of timing analysis and equivalency checks
• Prior experience with Cadence tools and flows

Perks & Benefits

• Paid vacation
• Paid holidays
• 401(k) plan with employer match
• Employee stock purchase plan
• A variety of medical, dental and vision plan options

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.

Requirements;

• Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
• Should possess intimate knowledge of DFT insertion flows
• Basic scan chain insertion using synthesis or other software tools
• Experience in compression scan insertion, LBIST and other scan technologies
• Intimate knowledge of memory build-in self-test (MBIST)
• Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
• Debug and Analysis of failures to improve fault coverage
• Verification of ATPG testbenches and debugging root cause of simulation mis-compares
• Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687
• Knowledge of timing analysis and equivalency checks would be added bonus
• Ability to work in collaborative team environment
• Prior experience with Cadence tools and flows is highly desirable
• Should be able to finish DFT tasks independently
• Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems
• Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers
• Self-driven and committed individual who can work in a fast-paced project environment

The annual salary range for San Jose, CA is $ 143,500 to $266,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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