Cadence is seeking a Sr Principal Firmware Engineer to join the DDR PHY IP Front End Design team. This role involves developing bare-metal firmware in C for DDR5 PHY using microcontrollers, collaborating with hardware designers and verification teams on training algorithms and co-verification plans. The engineer will also be responsible for debugging firmware in RTL simulations and on silicon bring-up boards. Key skills include knowledge of DDR5 JEDEC spec, C programming, scripting, and experience with EDA tools.