undefined ago • 3 Years + • Software Development & Engineering
Job Summary
Job Description
This role is for a Design Engineer 1 specializing in Digital Physical Design. Key responsibilities include block-level Netlist to GDS delivery and subsystem-level PnR and timing closure. The position requires hands-on experience in physical design and timing analysis, along with proficiency in scripting.
Must have:
Block level Netlist to GDS delivery
Subsystem level PnR and timing closure
3+ years of experience in PnR and STA
Handson experience in RTL/Netlist to GDS delivery of blocks
Good exposure to Placement, CTS and Routing techniques
Capable of doing PV and IREM fixes along with timing
Good exposure to Cadence EDA tool set needed for PD
TCL and PERL scripting knowledge and experience in writing the scripts
Good to have:
Complex blocks floorplan, PnR and STA
Complex IP integration like DDR and PCIe
Hands on experience in low power designs
Good understanding of DFT stitching
Exposure to any of 7/6nm, 5/4nm & 3/2nm technologies
Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.