Design Engineer I
Job Summary
Job Description
This Design Engineer I role at Cadence requires a candidate with strong knowledge of SCAN/ATPG/JTAG/MBIST and experience with chip tape out, including ATE bring up. The role involves gate-level simulations, experience with test structures for DFT, IP integration, and scan insertion techniques. The candidate will be responsible for Memory BIST generation and JTAG knowledge. The role also involves running block level and chip STA flows, resolving DFT issues, and using industry-standard tools like Cadence/Tessent. Strong teamwork, communication skills, and a sense of responsibility are essential for successful tape out and post-silicon bring up.
Must have:
- Knowledge of SCAN/ATPG/JTAG/MBIST
- Experience with chip tape out and ATE bring up
- Experience with gate level simulation
- Experience with test structures for DFT
Good to have:
- Experience with post-silicon bring up and debug on ATE
- Proficiency in industry standard tools (Cadence/Tessent tools)
- Knowledge of Perl/Tcl scripting skills
3 skills required
Job Details
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- BE/BTECH---1-4 yrs
- Very good knowledge on SCAN/ATPG/JTAG/MBIST
- Experience with one or more chip tape out that includes chip ATE bring up.
- Experience on gate level simulation with no timing and timing (SDF) simulations (ATPG/MBIST/JTAG)
- Experience in Test structures for DFT, IP integration, ATPG fault models, test point insertion, coverage improvement techniques.
- Experience in scan insertion techniques at block level and chip top level.
- Experience on Memory BIST generation, insertion, verification on RTL/Netlist level.
- Good knowledge and understanding in Analog PHY and Analog Macro tests.
- Good knowledge and understanding on JTAG for IEEE 1149.1/IEEE1149.6 standards.
- Good knowledge on test mode timing constraints
- Good knowledge about running block level and chip STA flows.
- Cross domain knowledge to resolve DFT issues with design, synthesis, physical design, STA team.
- Proficiency in industry standard tools for scan insertion, ATPG, MBIST and JTAG (preferable Cadence/Tessent tools)
- Experience with post-silicon bring up and debug on ATE.
- Good knowledge on Perl/Tcl scription skills
- Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization.
- High sense of responsibility and ownership within the team for successful tape out and post-silicon bring up of project.
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About The Company
Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
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