Staff Engineer, Physical Design

Your Team, Your Impact

As a Staff Engineer, Physical Design, you will be a key part of a highly skilled global team focused on designing next-generation optical module chips for the high-performance computing AI/ML architecture space. Our custom DSP solutions power critical infrastructure in markets such as data center, connectivity, and optical module. You will work at the forefront of advanced CMOS process technology, contributing to both physical design and the development of efficient design methodologies.

What You Can Expect

In this role, you will play an essential part in developing and implementing the physical design flow for high-performance, low-power cutting-edge chips. You will work on synthesis, place and route, PGV, and timing analysis for complex logic blocks, ensuring that they meet stringent performance, power, and area targets. Furthermore, you’ll be involved in full-chip floorplanning, partition and design planning activities. By enhancing and maintaining the Place and Route flow using industry-standard EDA tools, you’ll enable seamless tape-outs and help drive continued leadership in the semiconductor industry.

Your collaboration with the RTL design and global timing teams will ensure smooth end-to-end design processes and successful delivery of best-in-class products. As the industry evolves, your contributions to methodologies will drive optimization and innovation for future technologies.

What Can You Expect

• Physical Design Execution: Perform synthesis, floor planning, place and route, clock tree synthesis, PGV, and timing analysis on complex blocks. You will ensure that designs meet performance, power, and area goals across advanced technology nodes like 5nm, 3nm, and 2nm.
• Methodology Development: Work on Place and Route methodology for efficient and robust design processes, enhancing physical design flow. You will be tasked with maintaining and supporting these methodologies to ensure continued improvements in efficiency and accuracy.
• Timing and Logic ECOs: Develop and implement timing and logic Engineering Change Orders (ECOs) while closely collaborating with RTL teams to address congestion and timing issues.
• Cross-functional Collaboration: Work closely with the frontend design and global timing teams to resolve block-level timing issues, ensuring a smooth tape-out process.
• Innovative Challenges: Tackle complex, multi-disciplinary challenges and play a key role in driving technology advancements in optical DSP chip designs. Your role is a critical interface between backend design, frontend design, and methodology teams.

What We're Looking For

• Educational Background: Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience. Coursework and projects must include digital logic design, circuit testing, and timing analysis.
• Professional Experience: At least 2 years of related experience in physical design, with a proven track record of successful tape-outs, preferably top-level implementation. Experience with advanced technology nodes such as 5nm, 3nm, or below is highly desirable. Experience with chiplet-based architectures and full-chip physical design a plus. Experience in static timing analysis (STA), with a focus on timing closure is highly desirable.
• Hands-On Expertise: Strong experience with industry-standard EDA tools, including synthesis, floor planning, place and route, clock tree synthesis, timing closure, EMIR, and physical verification.
• Physical Design Methodologies: Proven experience working with RTL-to-GDS flows, including experience with digital logic and computer architecture using Verilog/VHDL. Familiarity with timing analysis and congestion resolution is crucial.
• Scripting Skills: Demonstrable proficiency in scripting languages such as Perl, tcl, and Python for automation and workflow enhancement.
• Communication & Teamwork: Excellent communication skills and a proven ability to work effectively in a collaborative, team-oriented environment.
• Problem-Solving: Drive and ability to troubleshoot and resolve complex timing and physical design issues at block and partition levels.