STCO PDK Development and Custom Layout Integration Engineer

Company:

Qualcomm Semiconductor Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Key Responsibilities

• Design and mask layout of test chips for heterogeneous integration, custom DRAM, silicon components, and passive device development.

• Technology benchmarking, design flow, and PDK development for heterogeneous integration.

• Foundry interface and design support for System-Technology Co-Optimization (STCO).

• Layout and design analysis for advanced technology benchmarks

• Custom layout analysis for product issue debugging.

Desired Skillset/Experience

• Mask layout, OPC experience
• Physical design and layout experience in sub-10nm silicon technology; hybrid-bonding, u-bump, RDL, and advanced packaging-related work experience is a plus.
• SVRF and TCL scripting.
• Test chip design and execution experience.
• PDK development experience (PEX, DRC, LVS).
• DFM development experience.
• Custom layout experience (Calibre, Cadence).
• Process integration and unit process development experience is a strong plus.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR
Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR
High School diploma or equivalent and 8+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

• 4+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).

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