Design Verification Engineer Graduate (Video Silicon IP) - 2026 Start (BS/MS)

ResponsibilitiesOur team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services. We are looking for talented individuals to join our team in 2026. As a graduate, you will get opportunities to pursue bold ideas, tackle complex challenges, and unlock limitless growth. Launch your career where inspiration is infinite at ByteDance Successful candidates must be able to commit to an onboarding date by end of year 2026. Please state your availability and graduation date clearly in your resume. Candidates can apply to a maximum of two positions and will be considered for jobs in the order you apply. The application limit is applicable to ByteDance and its affiliates' jobs globally. Applications will be reviewed on a rolling basis - we encourage you to apply early. Responsibilities - As a Design Verification engineer, you will be taking on an important role in helping deliver a Video Codec IP by generating test benches and running simulations. You will interface with architects and ASIC/FPGA design engineers to develop test plans, lead bug tracking, automate regression testing, and close coverage.

Qualifications

Minimum Qualifications

• Currently pursuing a Master's in computer science/electrical engineering or a related technical discipline
• Knowledge of modern verification methodologies, such as UVM/OVM.
• Good programming skills with SystemVerilog to work on constrained randomization and functional coverage model.
• Familiar with RTL design (SystemVerilog) and SVA (SystemVerilog Assertion)

Prefered Qualifications

• Familiar with at least one scripting language, such as Python/Perl.
• Familiar with SystemC, or DPI

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