Lead Application Engineer
Job Summary
Job Description
This role involves advanced SoC block or fullchip level implementation, covering hierarchical partition, floorplan, Synthesis, APR, Physical Verification, Power Integrity, and timing Signoff/ECO. The engineer will analyze and optimize timing and congestion using SDC/STA skills and advanced CTS techniques, as well as dynamic and leakage power with low power methodologies. Responsibilities also include top-level IO/bump/RDL routing, fullchip physical verification with advanced process nodes, and scripting for efficiency.
Must have:
- Complete advanced SoC block or fullchip level implementation from RTL to GDS
- Perform hierarchical partition, floorplan, Synthesis, APR, Physical Verification, Power Integrity, timing Signoff/ECO
- Analyze and optimize timing and congestion with SDC/STA skills and advanced CTS techniques
- Analyze and optimize dynamic and leakage power with advanced low power methodology
- Complete top level IO/bump/RDL routing and fullchip physical verification
- Use Tcl/Perl/Python to write scripts to improve work efficiency
- Master with 3+ years or Bachelor with 6+ years’ experience in IC design
- Ability to understand and articulate technical issues
- Working knowledge of programming languages
- Good knowledge of verilog/spice/sdc/upf/lef/def/spef
- Familiarity with shell/Perl/Tcl script language
Good to have:
- Knowledge of design products and their applications
- Effective communication and soft skills
- Familiarity with Genus/Innovus/Voltus/Tempus products
- Good communication in English and good work attitude
5 skills required
Job Details
Job Description:
- To complete advanced SoC block or fullchip level implementation from RTL to GDS, including hierarchical partition, floorplan, Synthesis, APR, Physical Verification, Power Integrity and timing Signoff/ECO.
- To well analysis and optimize timing and congestion with SDC/STA skill, advanced nodes knowledge, especial advanced CTS techniques
- To well analysis and optimize dynamic and leakage power with advanced low power methodology and real project experience
- To complete top level IO/bump/RDL routing and fullchip physical verification with advanced process nodes experience and Design Rule/IP/IO/STD application knowledge
- Use Tcl/Perl/Python to write scripts to improve work efficiency
Position Requirements:
- Master with 3+ years working experience or Bachelor with 6+ years’ experience in IC design.
- Ability to understand and articulate technical issues, (and knowledge of) design products and their applications.
- Requires working knowledge of one or more programming languages, and effective communication and soft skills.
- Be familiar with Genus/Innovus/Voltus/Tempus product is a plus.
- Good knowledge of verilog/spice/sdc/upf/lef/def/spef.
- Good communication in English and good work attitude.
- Be familiar with shell/Perl/Tcl etc. script language.
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About The Company
Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
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