Job Details:

Job Description: 

This position is within the Design Technology Platform (DTP) organization of Technology Development. At Intel, Design Technology Platform is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on innovative technologies. As part of the Design Technology Platform/Process Design Kit (PDK) group, you will join a highly motivated team of talented engineers solving challenging technical problems, enabling PDKs for Intel's most advanced process technologies, and drive PDKs towards industry standard methods and ease of use for the end customers. The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors, and product design teams to develop and deliver high quality technology collaterals, models, and enablement of EDA tools. Responsibilities of this role focuses on PDK Development: Develops, maintains and ensures quality assurance of process design kit (PDK) collateral, including PDK Runset, PDK Extraction, PDK Custom Tech File and Library. #designenablement

Qualifications:

The candidate must possess minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork class research and or relevant previous job and or internship experiences. Minimum Qualifications: Bachelor/Master in Electrical / Electronics Engineering, Computer Engineering, Computer Science, or other related Electrical Scientific STEM field. 6+ months of work or educational experience in at least one of the following areas: Unix/Linux operating system Programming or scripting in at least one of: C++, Python, Ruby, Perl, Tcl, SKILL CMOS device physics, process technology and design rules Preferred Qualifications: Experience with working in software repository management tools like Git Knowledge of DRC/LVS/Extraction runsets Knowledge in semiconductor device physics, models, parasitic extraction, and technology scaling Familiarity with VLSI design process, reliability verification, ESD concepts, standard cell library, and memory architectures Familiarity with custom layout design of analog, RF, or digital circuits on advanced process technology nodes Working knowledge of EDA tools (Synopsys ICV, Siemens/Mentor Calibre, Cadence Pegasus, Virtuoso or Custom Compiler, Cadence Innovus, Synopsys Fusion Compiler or Siemens Aprisa tools)

          

Job Type:

College Grad

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.