Principal DFT Engineer

• Senior DFT engineer with 10+ yrs experience in SoC DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG, LBIST.
• BE/ME/B.Tech/M.Tech from reputed institutes with 1st class degree and minimum of 5yrs of relevant industry experience
• The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools.
• The engineer needs to have hands-on experience in scan insertion, JTAG, LBIST, ATPG DRC and coverage analysis, Simulation debug with timing/SDF.
• Must have worked on one SoC at least, from start to end.
• Must be proactive, collaborative and detail-oriented capable of exercising independent judgment
• The engineer with experience on debug and root cause the problem in simulation failures
• Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills
• Show an engaged curiosity, a will to understand the mechanisms behind the effects, an eagerness to constantly learn and improve

Career Development Opportunities

Bright Minds. Bright Futures.

We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills.

Commitment At NXP.

We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality.