SoC Physical Design Engineer

6 Hours ago • 3-7 Years • $139,710 PA - $197,230 PA

Job Summary

Job Description

The SoC Physical Design Engineer will research, design, develop, and test lead Intel designs, contributing to reimagining SoC building in the semiconductor industry. Responsibilities include physical design implementation from RTL to GDS, physical synthesis, floor planning, place and route, clock tree synthesis, multiple power domain analysis, verification and signoff, and participation in design methodology improvements. The role involves performance optimization and collaboration with process teams. The ideal candidate needs to have strong problem-solving skills, excellent interpersonal skills, attention to detail, and the ability to work in a team. This role will also be eligible for a hybrid work model.
Must have:
  • Physical synthesis, place and route with Synopsys or Cadence tools.
  • Static timing analysis constraint understanding and generation.
  • Multiple Power Domain analysis using standard Power Formats UPF or CPF.
Good to have:
  • Experience in physical design using industry EDA tools.
  • Experience in backend design and/or integration.
  • Product development on leading edge process nodes.
  • Experience in Python/Perl/TCL programming languages
Perks:
  • Competitive pay.
  • Stock.
  • Bonuses.
  • Health, retirement, and vacation benefits

Job Details

Job Details:

Job Description: 

We are looking for a SoC Physical Design Engineer, who is ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology.


Your responsibilities may include but not be limited to:

  • Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.

  • Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools.

  • Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF.

  • Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking.

  • Analyzes results and makes recommendations to fix violations for current and future product architecture.

  • Participating in the development and improvement of physical design methodologies and flow automation.

  • Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs.


The ideal candidate should exhibit behavioral traits that indicate:

  • Self-motivator with strong problem-solving skills.

  • Excellent interpersonal skills, including written, verbal, and presentation communications.

  • Attention to detail and organizational skills.

  • Ability to work as part of a team and collaborate in a high-paced atmosphere.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • Bachelor's degree in electrical engineering, Computer Engineering or related field with 5+ years of relevant experience OR

  • Master's degree Electrical Engineering, Computer Engineering or related field with 3+ years of relevant experience

The relevant experience would include one of the following areas:

  • Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.

  • Static timing analysis constraint understanding and generation, clock stamping, and timing closure.

  • Multiple Power Domain analysis using standard Power Formats UPF or CPF.


Preferred Qualifications:

  • 6+ years of experience in physical design using industry EDA tools.

  • 7+ years of experience in backend design and/or integration

  • Product development and delivery on leading edge process nodes

  • Experience in Python/Perl/TCL programming languages

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Oregon, Hillsboro

Additional Locations:

Business group:

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$139,710.00-$197,230.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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About The Company

Intel provides reasonable accommodation to applicants and employees. For more information on our Reasonable Accommodation process, please clickhere.When you use this site, Intel Corporation uses cookies to improve your online experience. For more information, visit ourCookie Notice.To view our candidate privacy notice, please clickhere.

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