Video Design Verification Engineer

3 Months ago • 3-13 Years

Software Development & Engineering

Job Description

This position is for a Video Design Verification Engineer at Qualcomm. The responsibilities include working on coverage-driven module verification, developing testbenches using System Verilog and UVM, debugging failures, and working with C-based reference models. The engineer will also be involved in assertion development, scripting, and interacting with designers and other verification engineers. The role requires experience in video pipeline verification and familiarity with EDA tools like IUS, VCS, and Verdi. The job requires strong technical skills and the ability to collaborate with a team.

Good To Have:

Prior experience with video pipeline
Knowledge of Tensilica
Experience in C-based system modelling

Must Have:

Experience with coverage-driven module verification
Strong skills in System Verilog, UVM
Experience in testbench development
Ability to debug failures using Verdi and log files
Experience with assertion development
Familiarity with EDA tools (IUS, VCS, Verdi)
Exposure to scripting (Perl, Python)

Add these skills to join the top 1% applicants for this job

problem-solving

team-player

game-texts

python

perl

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Looking for candidates between 3 to 13 years of experience.
Worked on coverage driven module verification.
Strong in System Verilog, UVM
Sound experience in testbench (stimulus, agent, monitor, checker) development.
Failure debugging with Verdi & log file.
Worked in the verification having c based reference model inside the testbench
Experience with assertion development.
Familiar with the EDA tools IUS, VCS, Verdi etc.
Exposure in scripting(perl, Python).
Good team player. Need to interact with the designers and other verification engineers proactively.
Prior experience with video pipeline is added advantage.
Knowledge of tensilica
Worked with sub-system verification with tensilica
Experience in C based system modelling.
Debug with C based reference model.
Have exposure to the other verification tasks : gate level simulation, Power aware simulation, formal verification, sub-system verification and emulation.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

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